AD9516-0_07 AD [Analog Devices], AD9516-0_07 Datasheet
AD9516-0_07
Related parts for AD9516-0_07
AD9516-0_07 Summary of contents
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... The AD9516-0 is specified for operation over the industrial range of −40°C to +85°C. 1 AD9516 is used throughout to refer to all the members of the AD9516 family. However, when AD9516-0 is used it is referring to that specific member of the AD9516 family. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. ...
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... AD9516-0 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications..................................................................................... 4 Power Supply Requirements ....................................................... 4 PLL Characteristics ...................................................................... 4 Clock Inputs .................................................................................. 6 Clock Outputs ............................................................................... 6 Timing Characteristics ................................................................ 7 Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used) ........................................................................ 8 Clock Output Absolute Phase Noise (Internal VCO Used).... 9 Clock Output Absolute Time Jitter (Clock Generation Using Internal VCO) ...
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... The Instruction Word (16 Bits).................................................53 MSB/LSB First Transfers ............................................................53 REVISION HISTORY 4/07—Revision 0: Initial Version Register Map Overview ..................................................................56 Register Map Descriptions.............................................................60 Application Notes............................................................................79 Using the AD9516 Outputs for ADC Clock Applications ....79 LVPECL Clock Distribution......................................................79 LVDS Clock Distribution...........................................................79 CMOS Clock Distribution.........................................................80 Outline Dimensions........................................................................81 Ordering Guide ...........................................................................81 Rev Page ...
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... AD9516-0 SPECIFICATIONS Typical (typ) is given for 3.3 V ± 5 S_LVPECL unless otherwise noted. Minimum (min) and maximum (max) values are given over full V POWER SUPPLY REQUIREMENTS Table 1. Parameter Min Typ V 3.135 3 2.375 S_LVPECL RSET Pin Resistor 4.12 CPRSET Pin Resistor 5 ...
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... Rev Page AD9516-0 Test Conditions/Comments Antibacklash pulse width = 1.3 ns, 2.9 ns Antibacklash pulse width = 6.0 ns 0x17<1:0> = 01b 0x17<1:0> = 00b; 0x17<1:0> = 11b 0x17<1:0> = 10b Programmable With CP = 5.1 kΩ RSET 0.5 < CP < ...
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... AD9516-0 Parameter 2 PLL DIGITAL LOCK DETECT WINDOW Required to Lock (Coincidence of Edges) Low Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 6 ns Unlock After Lock (Hysteresis) Low Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 6 ns) 1 REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition. ...
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... Rev Page AD9516-0 Test Conditions/Comments Single-ended; termination = 10 pF see Figure load @ 1 mA load Test Conditions/Comments Termination = 50 Ω − level = 810 mV S 20% to 80%, measured differentially 80% to 20%, measured differentially See Figure 42 See Figure 44 Termination = 100 Ω differential; 3.5 mA ...
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... AD9516-0 Parameter Delay Variation with Temperature 5 Short Delay Range Zero Scale Full Scale Long Delay Range 5 Zero Scale Full Scale 1 This is the difference between any two similar delay paths while operating at the same voltage and temperature. 2 Corresponding CMOS drivers set to A for noninverting, and B for inverting. ...
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... Rev Page AD9516-0 Test Conditions/Comments Input slew rate > 1 V/ns Distribution section only; does not include PLL and VCO Input slew rate > 1 V/ns Input slew rate > 1 V/ns Test Conditions/Comments Internal VCO; direct to LVPECL output ...
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... AD9516-0 Parameter VCO = 2.55 GHz; OUTPUT = 2.55 GHz @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset @ 10 MHz Offset @ 40 MHz Offset CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO) Table 8. Parameter LVPECL OUTPUT ABSOLUTE TIME JITTER VCO = 2.95 GHz; LVPECL = 491.52 MHz; PLL LBW = 75 kHz VCO = 2.95 GHz ...
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... Distribution section only; does not include PLL and VCO; rising edge of clock signal 350 f rms Calculated from SNR of ADC method S Rev Page AD9516-0 Unit Test Conditions/Comments Distribution section only; does not include PLL and VCO; rising edge of clock signal f rms ...
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... AD9516-0 DELAY BLOCK ADDITIVE TIME JITTER Table 13. Parameter DELAY BLOCK ADDITIVE TIME JITTER 1 100 MHz Output Delay (1600 μA, 1C) Fine Adj. 000000 Delay (1600 μA, 1C) Fine Adj. 101111 Delay (800 μA, 1C) Fine Adj. 000000 Delay (800 μA, 1C) Fine Adj. 101111 Delay (800 μA, 4C) Fine Adj. 000000 Delay (800 μ ...
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... On-chip capacitance; used to calculate RC time constant for analog lock detect readback; use a pull-up resistor 1.02 MHz Frequency above which the monitor always indicates the presence of the reference 8 kHz Frequency above which the monitor always indicates the presence of the reference 1.6 V 260 mV Rev Page AD9516-0 ...
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... AD9516-0 POWER DISSIPATION Table 17. Parameter POWER DISSIPATION, CHIP Power-On Default Full Operation; CMOS Outputs at 229 MHz Full Operation; LVDS Outputs at 200 MHz PD Power-Down PD Power-Down, Maximum Sleep V Supply CP POWER DELTAS, INDIVIDUAL FUNCTIONS VCO Divider REFIN (Differential) REF1, REF2 (Single-Ended) VCO PLL Channel Divider ...
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... LVDS t CMOS Figure 2. CLK/ CLK to Clock Output Timing, DIV = 1 DIFFERENTIAL 80% LVPECL 20 Figure 3. LVPECL Timing, Differential t FP Rev Page DIFFERENTIAL 80% LVDS 20 Figure 4. LVDS Timing, Differential SINGLE-ENDED 80% CMOS 10pF LOAD 20 Figure 5. CMOS Timing, Single-Ended Load AD9516-0 ...
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... AD9516-0 ABSOLUTE MAXIMUM RATINGS Table 18. With Parameter or Pin Respect to VS, VS_LVPECL GND VCP GND REFIN, REFIN GND REFIN REFIN RSET GND CPRSET GND CLK, CLK GND CLK CLK SCLK, SDIO, SDO, CS GND OUT0, OUT0, OUT1, GND OUT1, OUT2, OUT2, OUT3, OUT3, OUT4, ...
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... VS 12 CLK 13 CLK SCLK 16 LVPECL LVPECL Figure 6. Pin Configuration < Rev Page OUT6 (OUT6A) 47 OUT6 (OUT6B) 46 OUT7 (OUT7A) 45 OUT7 (OUT7B) 44 GND 43 OUT2 42 OUT2 41 VS_LVPECL 40 OUT3 39 OUT3 GND 36 OUT9 (OUT9B) 35 OUT9 (OUT9A) 34 OUT8 (OUT8B) 33 OUT8 (OUT8A) < 5 AD9516-0 ...
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... AD9516-0 Pin No. Mnemonic Description 55 OUT0 LVPECL Output; One Side of a Differential LVPECL Output. 53 OUT1 LVPECL Output; One Side of a Differential LVPECL Output. 52 OUT1 LVPECL Output; One Side of a Differential LVPECL Output. 43 OUT2 LVPECL Output; One Side of a Differential LVPECL Output. 42 OUT2 LVPECL Output ...
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... Rev Page 2.55 2.65 2.75 2.85 VCO FREQUENCY (GHz) Figure 10. VCO K vs. Frequency VCO 5.0 4.5 4.0 3.5 PUMP DOWN PUMP UP 3.0 2.5 2.0 1.5 1.0 0 0.5 1.0 1.5 2.0 2.5 VOLTAGE ON CP PIN (V) Figure 11. Charge Pump Characteristics @ V 5.0 4.5 4.0 3.5 PUMP DOWN PUMP UP 3.0 2.5 2.0 1.5 1.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOLTAGE ON CP PIN (V) Figure 12. Charge Pump Characteristics @ V AD9516-0 2.95 3 4.0 4.5 5 ...
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... AD9516-0 –140 –145 –150 –155 –160 –165 –170 0.1 1 PFD FREQUENCY (MHz) Figure 13. PFD Phase Noise Referred to PFD Input vs. PFD Frequency –210 –212 –214 –216 –218 –220 –222 –224 0 0.5 1.0 1.5 SLEW RATE (V/ns) Figure 14. PLL Figure of Merit (FOM) vs. Slew Rate at REFIN/ REFIN 2.1 1.9 1.7 1.5 1.3 1.1 0.9 2.55 2.60 2.65 2.70 2.75 2.80 FREQUENCY (GHz) Figure 15. VCO Tuning Voltage vs. Frequency – ...
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... Figure 21. LVDS Output (Differential) @ 100 MHz 0.4 0.2 0 –0.2 –0 Figure 22. LVDS Output (Differential) @ 800 MHz 2.8 1.8 0.8 –0 2.8 1.8 0.8 –0 Rev Page AD9516 TIME (ns 100 TIME (ns) Figure 23.CMOS Output @ 25 MHz TIME (ns) Figure 24. CMOS Output @ 250 MHz 12 ...
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... AD9516-0 1600 1400 1200 1000 800 0 1 FREQUENCY (GHz) Figure 25. LVPECL Differential Swing vs. Frequency 700 600 500 0 100 200 300 400 500 FREQUENCY (MHz) Figure 26. LVDS Differential Swing vs. Frequency 100 200 300 OUTPUT FREQUENCY (MHz) Figure 27. CMOS Output Swing vs. Frequency and Capacitive Load ...
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... Figure 35. Phase Noise (Additive) LVDS @ 800 MHz, Divide-by-2 –120 –130 –140 –150 –160 –170 10 10M 100M Figure 36. Phase Noise (Additive) CMOS @ 50 MHz, Divide-by-20 Rev Page AD9516-0 100 1k 10k 100k 1M 10M FREQUENCY (Hz) 100 1k 10k 100k 1M 10M FREQUENCY (Hz) 100 ...
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... AD9516-0 –100 –110 –120 –130 –140 –150 –160 10 100 1k 10k 100k FREQUENCY (Hz) Figure 37. Phase Noise (Additive) CMOS @ 250 MHz, Divide-by-4 –120 –130 –140 –150 –160 1k 10k 100k 1M FREQUENCY (Hz) Figure 38. Phase Noise (Absolute) Clock Generation; Internal VCO @ 2.7 GHz; PFD = 15.36 MHz; LBW = 110 kHz; LVPECL Output = 122.88 MHz – ...
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... In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter. Rev Page AD9516-0 ...
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... REFIN (REF2) LOW DROPOUT BYPASS REGULATOR (LDO) LF VCO CLK CLK PD DIGITAL SYNC LOGIC RESET SCLK SERIAL SDIO CONTROL SDO PORT CS AD9516-0 VS GND RSET REFMON DISTRIBUTION REFERENCE R PROGRAMMABLE DIVIDER R DELAY VCO STATUS PROGRAMMABLE A/B N DELAY PRESCALER COUNTERS N DIVIDER DIVIDE ...
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... THEORY OF OPERATION OPERATIONAL CONFIGURATIONS The AD9516 can be configured in several ways. These configurations must be setup by loading the control registers (Table 51 and Table 52 through Table 61). Each section or function must be individually programmed by setting the appropriate bits in the corresponding control register or registers. High Frequency Clock Distribution—CLK or External VCO > ...
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... REGULATOR (LDO) PRESCALER LF VCO CLK CLK PD DIGITAL SYNC LOGIC RESET SCLK SERIAL SDIO CONTROL SDO PORT CS AD9516-0 Figure 42. High Frequency Clock Distribution or External VCO > 1600 MHz GND RSET REFMON DISTRIBUTION REFERENCE R PROGRAMMABLE DIVIDER R DELAY VCO STATUS A/B PROGRAMMABLE COUNTERS N DELAY N DIVIDER ...
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... Initiate VCO calibration. 0x232<0> 0x1E0<2:0> VCO divider set to divide-by-2, divide-by-3, divide-by-4, divide-by-5, and divide-by-6. 0x1E1<0> Use the VCO divider as source for distribution section. 0x1E1<1> VCO selected as the source. Rev Page AD9516-0 CP ...
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... LOW DROPOUT BYPASS REGULATOR (LDO) PRESCALER LF VCO CLK CLK PD DIGITAL SYNC LOGIC RESET SCLK SERIAL SDIO CONTROL SDO PORT CS AD9516-0 GND RSET REFMON DISTRIBUTION REFERENCE R PROGRAMMABLE DIVIDER R DELAY VCO STATUS PROGRAMMABLE A/B N DELAY COUNTERS N DIVIDER DIVIDE ...
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... PLL. Make sure to select the proper PFD polarity for the VCO/VCXO being used. Table 27. Setting the PFD Polarity Register Function 0x10<7> PFD polarity positive (higher control voltage produces higher frequency) 0x10<7> PFD polarity negative (higher control voltage produces lower frequency) Rev Page AD9516-0 ...
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... LOW DROPOUT BYPASS REGULATOR (LDO) PRESCALER LF VCO CLK CLK PD DIGITAL SYNC LOGIC RESET SCLK SERIAL SDIO CONTROL SDO PORT CS AD9516-0 GND RSET REFMON DISTRIBUTION REFERENCE R PROGRAMMABLE DIVIDER R DELAY VCO STATUS PROGRAMMABLE A/B N DELAY COUNTERS N DIVIDER DIVIDE ...
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... ADIsimCLK™ (V1.2 or later free program that can help with the design and exploration of the capabilities and features of the AD9516, including the design of the PLL loop filter available at www.analog.com/clocks. Phase Frequency Detector (PFD) The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them ...
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... PLL Reference Inputs The AD9516 features a flexible PLL reference input circuit that allows either a fully differential input or two separate single- ended inputs. The input frequency range for the reference inputs is specified in Table 2. Both the differential and the single-ended inputs are self-biased, allowing for easy ac coupling of input signals ...
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... The prescaler modes of operation are given in Table 53, 0x16<2:0>. Not all modes are available at all frequencies (see Table 2). When operating the AD9516 in dual modulus mode (P//P + 1), the equation used to relate input reference frequency to VCO output frequency is ...
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... use the dual modulus mode 4/5 with and B Counters The AD9516 B counter can be bypassed (B = 1). This B counter bypass mode is only valid when using the prescaler in FD mode. When the divide is a fixed divide 16, or 32. ...
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... The number of consecutive PFD cycles required for lock is programmable (0x18<6:5>). Analog Lock Detect (ALD) The AD9516 provides an ALD function that may be selected for use at the LD pin. There are two versions of ALD: • N-channel open-drain lock detect. This signal requires a pull-up resistor to positive supply, VS. The output is normally high with short, low going pulses ...
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... AD9516-0 Holdover The AD9516 PLL has a holdover function. Holdover is implemented by putting the charge pump into a high impedance state. This is useful when the PLL reference clock is lost. Holdover mode allows the VCO to maintain a relatively constant frequency even though there is no reference clock. ...
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... Frequency Status Monitors The AD9516 contains three frequency status monitors that are used to indicate if the PLL reference (or references in the case of single-ended mode) and the VCO have fallen below a threshold frequency ...
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... REFIN clock. The calibration requires that the PLL be set up properly to lock the PLL loop and that the REFIN clock be present. During the first initialization after a power- reset of the AD9516, a VCO calibration sequence is initiated by setting 0x18<0> = 1b. This can be done as part of the initial setup, before executing update registers (0x232<0> = 1b). ...
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... The divider outputs can also be set to start high or start low. Internal VCO or External CLK as Clock Source The clock distribution of the AD9516 has two clock input sources: internal VCO or an external clock connected to the CLK/ CLK pins. Either the internal VCO or CLK must be chosen as the source of the clock signal to distribute ...
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... AD9516-0 To connect the LVPECL outputs directly to the internal VCO or CLK, the VCO divider must be selected as the source to the distribution section, even if no channel uses it. Either the internal VCO or the CLK can be selected as the source for the direct to output routing. Table 31. Settings for Routing VCO Divider Input Directly ...
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... VCO is connected direct to output, the duty cycle is 50%. If the 50% CLK input is routed direct to output, the duty cycle of the output is the same as the CLK input. 50%; requires 50%; requires Rev Page AD9516-0 D Output Duty Cycle DCCOFF = 1 DCCOFF = 0 1 (divider ...
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... AD9516-0 Phase Offset or Coarse Time Delay (0, 1, and 2) Each channel divider allows for a phase offset coarse time delay programmed by setting register bits (see Table 38). These settings determine the number of cycles (successive rising edges) of the channel divider input frequency by which to offset, or delay, the rising edge of the output of the divider ...
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... Output Duty Cycle 50% 33.3% 40 1)/ X X.1 X 1)/ X X.1 X 1)/ X X.2 X 1)/ X X.2 X.2 Rev Page AD9516 Output X.1 X.2 Duty Cycle X.1 X.1 X Even, Odd Even, Odd Even, Odd Even, Odd (N (N Even, Odd Even, Odd ...
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... AD9516-0 Table 43. Divider 3, Divider 4 Duty Cycle; VCO Divider Used; Duty Cycle Correction On (DCCOFF = 0); VCO Divider Input Duty Cycle = X.1 X.2 VCO Divider X.1 X.1 X.2 X.2 Even 1 1 Odd = Odd = Even Even X.1 X.1 Even Odd X.1 X.1 Odd Even X.1 X.1 Odd ...
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... A slower ramp CMOS time produces more time jitter. Synchronizing the Outputs—SYNC Function The AD9516 clock outputs can be synchronized to each other. Outputs can be individually excluded from synchronization. Synchronization consists of setting the nonexcluded outputs to a preset set of static conditions and subsequently releasing these ...
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... SYNC signal with respect to the clock edges inside the AD9516. The delay from the SYNC rising edge to the beginning of synchronized output clocking is between 14 and 15 cycles of clock at the ...
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... SYNC operation. Between outputs and after synchronization, this allows for the setting of phase offsets. The AD9516 outputs are in pairs, sharing a channel divider per pair (two pairs of pairs, four outputs, in the case of CMOS). The synchronization conditions apply to both outputs of a pair. ...
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... LVPECL output circuitry from damage that could be caused by certain termination and load configurations when tristated. Because this is not a complete power-down, it can be called sleep mode. When the AD9516 power-down, the chip is in the following state: • The PLL is off (asynchronous power-down). ...
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... Distribution Power-Down section). Individual Circuit Block Power-Down Other AD9516 circuit blocks (such as CLK, REF1, and REF2) can be powered down individually. This gives flexibility in configuring the part for power savings whenever certain chip functions are not needed ...
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... SDIO 22 Figure 60. Serial Control Port GENERAL OPERATION OF SERIAL CONTROL PORT A write or a read operation to the AD9516 is initiated by pulling CS low. CS stall high is supported in modes where three or fewer bytes of data (plus instruction data) are transferred (see Table 47). In these modes, CS can temporarily return high on any byte boundary, allowing time for the system controller to process the next byte ...
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... In MSB first mode, subsequent bytes increment the address. MSB/LSB FIRST TRANSFERS The AD9516 instruction word and byte data can be MSB first or LSB first. Any data written to 0x000 must be mirrored, the upper four bits (<7:4>) with the lower four bits (<3:0>). This makes it irrelevant whether LSB first or MSB first is in effect ...
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... AD9516-0 Table 49. Serial Control Port, 16-Bit Instruction Word, MSB First MSB I15 I14 I13 I12 R A12 = 0 CS SCLK DON'T CARE SDIO R A12 A11 A10 DON'T CARE 16-BIT INSTRUCTION HEADER Figure 62. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes Data ...
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... Minimum period that SCLK should Logic High state HI t Minimum period that SCLK should Logic Low state LO t SCLK to valid SDIO and SDO (see Figure 65 CLK Figure 67. Serial Control Port Timing—Write Rev Page AD9516 ...
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... AD9516-0 REGISTER MAP OVERVIEW Table 51. Register Map Overview Addr Bit 7 (Hex) Parameter (MSB) Bit 6 Serial Port Configuration 00 Serial Port SDO LSB First Configuration Active Read Back Control PLL 10 PFD and PFD Charge Pump Polarity 11 R Counter 12 Blank 13 A Counter ...
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... CMOS B LVDS/CMOS Output Polarity OUT9 LVDS/ OUT9 OUT9 Select CMOS CMOS B LVDS/CMOS Output Polarity Rev Page AD9516-0 Bit 2 Bit 1 Bit 0 (LSB) OUT6 Delay Bypass OUT6 Ramp Current OUT7 Delay Bypass OUT7 Ramp Current OUT8 Delay Bypass OUT8 Ramp Current OUT9 Delay ...
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... AD9516-0 Addr Bit 7 (Hex) Parameter (MSB) Bit 6 144 to 18F LVPECL Channel Dividers 190 Divider 0 Divider 0 Low Cycles (PECL) 191 Divider 0 Divider 0 Bypass Nosync 192 Blank 193 Divider 1 Divider 1 Low Cycles (PECL) 194 Divider 1 Divider 1 Bypass Nosync 195 Blank 196 Divider 2 Divider 2 Low Cycles ...
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... Power Down and Sync 231 Update All Registers 232 Update All Registers Bit 5 Bit 4 Bit 3 Reserved Blank Blank Rev Page AD9516-0 Bit 2 Bit 1 Bit 0 (LSB) Power- Power- Soft Sync Down Sync Down Distribution Reference Reserved Update All Registers (Self- ...
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... AD9516-0 REGISTER MAP DESCRIPTIONS Table 52 through Table 61 are a detailed description of each of the control register functions. The registers are listed by hexadecimal address. Reference to a specific bit or range of bits within a register is indicated by angle brackets. Example: <3> refers to Bit 3, while <5:2> refers to the range of bits from Bit 5 through Bit 2. ...
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... A and B counters. <4> I (mA 0.6 1 1.2 0 1.8 1 2.4 0 3.0 1 3.6 0 4.2 1 4.8 Charge Pump Mode High impedance state. Force source current (pump up). Force sink current (pump down). Normal operation. Mode Normal operation. Asynchronous power-down. Normal operation. Synchronous power-down. supply voltage. CP /2. CP Rev Page AD9516-0 ...
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... AD9516-0 Reg. Addr (Hex) Bit(s) Name Description 16 <4> Reset All Reset R, A, and B counters. Counters <4> normal. <4> reset R, A, and B counters. 16 <3> B Counter B counter bypass. This is valid only when operating the prescaler in FD mode. Bypass <3> normal. <3> counter is set to divide-by-1. This allows the prescaler setting to determine the divide for the N divider ...
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... Selected reference (Low = REF2, High = REF1 LVL Digital lock detect (DLD) (active low LVL Holdover active (active low LVL LD pin comparator output (active low). Antibacklash Pulse Width (ns) 2.9 1.3 6.0 2.9 PFD Cycles to Determine Lock 255 (default) Rev Page AD9516-0 ...
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... AD9516-0 Reg. Addr (Hex) Bit(s) Name Description 19 <7:6> <7> <6> Counters 0 0 SYNC Pin 0 1 Reset <5:3> R Path Delay <5:3> R Path Delay (see Table 2). 19 <2:0> N Path Delay <2:0> N Path Delay (see Table 2). 1A <6> Reference Sets the reference (REF1/REF2) frequency monitor’s detection threshold frequency. This does not affect Frequency the VCO frequency monitor’ ...
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... LVL LD pin comparator output (active high LVL VS (PLL supply DYN REF1 clock (differential reference when in differential mode DYN REF2 clock (not available in differential mode DYN Selected reference to PLL (differential reference when in differential mode). Rev Page AD9516-0 ...
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... AD9516-0 Reg. Addr (Hex) Bit(s) Name Description <4> <3> <2> <1> <7> Disable Disable or enable the switchover deglitch circuit. Switchover <7> enable switchover deglitch circuit. Deglitch <7> disable switchover deglitch circuit. ...
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... Readback register: indicates if the frequency of the signal at REF2 is greater than the threshold frequency Frequency > set by Register 0x1A<6>. Threshold <1> REF1 frequency is less than threshold frequency. <1> REF1 frequency is greater than threshold frequency. 1F <0> Digital Lock Readback register: digital lock detect. Detect <0> PLL is not locked. <0> PLL is locked. Rev Page AD9516-0 ...
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... AD9516-0 Table 54. Fine Delay Adjust: OUT6 to OUT9 Reg. Addr (Hex) Bit(s) Name Description A0 <0> OUT6 Delay Bypass or use the delay function. Bypass <0> use delay function. <0> bypass delay function. A1 <5:3> OUT6 Ramp Selects the number of ramp capacitors used by the delay function. The combination of number of the Capacitors capacitors and the ramp current sets the delay full scale ...
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... OUT9 Delay Bypass or use the delay function. Bypass <0> use delay function. <0> bypass delay function. 0 200 1 400 0 600 1 800 0 1000 1 1200 0 1400 1 1600 200 1 400 0 600 1 800 0 1000 1 1200 0 1400 1 1600 Rev Page AD9516-0 ...
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... AD9516-0 Reg. Addr (Hex) Bit(s) Name Description AA <5:3> OUT9 Ramp Selects the number of ramp capacitors used by the delay function. The combination of the number of Capacitors capacitors and the ramp current sets the delay full scale. <5> <4> <3> Number of Capacitors <2:0> OUT9 Ramp Ramp current for the delay function ...
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... Partial power-down, reference on; use only if there are no external load resistors. Partial power-down, reference on, safe LVPECL power-down. Total power-down, reference off; use only if there are no external load resistors (mV) OD 400 600 780 960 Rev Page AD9516-0 Output On Off Off Off Output On Off Off Off Output ...
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... AD9516-0 Reg. Addr (Hex) Bit(s) Name Description F4 <1:0> OUT4 LVPECL power-down modes. Power-Down <1> <0> Mode <4> OUT5 Invert Sets the output polarity. <4> noninverting. <4> inverting. F5 <3:2> OUT5 LVPECL Sets the LVPECL output differential voltage (V Differential <3> <2> V Voltage <1:0> OUT5 LVPECL power-down modes. ...
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... Set output current level in LVDS mode. This has no effect in CMOS mode. <2> <1> Current (mA) Recommended Termination (Ω 1.75 100 0 1 3.5 100 Rev Page AD9516-0 OUT7 (LVDS) Noninverting Noninverting Noninverting Noninverting Inverting Inverting Inverting Inverting OUT8 (LVDS) Noninverting Noninverting Noninverting Noninverting Inverting Inverting Inverting Inverting ...
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... AD9516-0 Reg. Addr (Hex) Bit(s) Name 142 <0> OUT8 Power-Down 143 <7:5> OUT9 Output Polarity 143 <4> OUT9 CMOS B 143 <3> OUT9 Select LVDS/CMOS 143 <2:1> OUT9 LVDS Output Current 143 <0> OUT9 Power-Down Table 57. LVPECL Channel Dividers Reg. Addr (Hex) Bit(s) Name 190 <7:4> Divider 0 Low Cycles 190 < ...
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... SYNC signal. Force divider output to high. This requires that nosync also be set. <5> divider output forced to low. <5> divider output forced to high. Selects clock output to start high or start low. <4> start low. <4> start high. Phase offset. Rev Page AD9516-0 ...
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... AD9516-0 Reg. Addr (Hex) Bit(s) Name 198 <1> Divider 2 Direct to Output 198 <0> Divider 2 DCCOFF Table 58. LVDS/CMOS Channel Dividers Reg. Addr (Hex) Bit(s) Name 199 <7:4> Low Cycles Divider 3.1 199 <3:0> High Cycles Divider 3.1 19A <7:4> Phase Offset Divider 3.2 19A <3:0> Phase Offset Divider 3.1 19B <7:4> Low Cycles Divider 3.2 19B < ...
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... Select external CLK as input to VCO divider. <1> Select VCO as input to VCO divider; cannot bypass VCO divider when this is selected. Bypass or use the VCO divider. <0> use VCO divider. <0> bypass VCO divider; cannot select VCO as input when this is selected. Rev Page AD9516-0 Divide ...
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... AD9516-0 Table 60. System Reg. Addr (Hex) Bit(s) Name 230 <2> Power-Down Sync 230 <1> Power-Down Distribution Reference 230 <0> Soft SYNC Table 61. Update All Registers Reg. Addr (Hex) Bit(s) Name Description 232 <0> Update All This bit must be set transfer the contents of the buffer registers into the active registers. This happens Registers on the next SCLK rising edge. This bit is self-clearing ...
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... LVDS CLOCK DISTRIBUTION 12 The AD9516 provides four clock outputs (OUT6 to OUT9) that 10 are selectable as either CMOS or LVDS level outputs. LVDS is a differential output option that uses a current mode output stage. 8 The nominal current is 3.5 mA, which yields 350 mV output swing across a 100 Ω resistor. The LVDS output meets or 6 exceeds all ANSI/TIA/EIA-644 specifications ...
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... Because of the limitations of single-ended CMOS clocking, consider using differential outputs when driving high speed signals over long traces. The AD9516 offers both LVPECL and LVDS outputs that are better suited for driving long traces where the inherent noise immunity of differential signaling provides superior performance for clocking converters ...
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... Body, Very Thin Quad CP-64-4 Dimensions shown in millimeters Package Description 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) Evaluation Board Rev Page 0.30 0.25 0.60 MAX 0.18 PIN 1 INDICATOR 64 1 6.35 EXPOSED PAD 6.20 SQ (BOTTOM VIEW) 6. 7.50 REF Package Option CP-64-4 CP-64-4 AD9516-0 ...
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... AD9516-0 NOTES Rev Page ...
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... NOTES Rev Page AD9516-0 ...
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... AD9516-0 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06419-0-4/07(0) Rev Page ...