AD9511BCPZ-REEL AD [Analog Devices], AD9511BCPZ-REEL Datasheet - Page 9

• Manufacturer Part Number: AD9511BCPZ-REEL
• Description: 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs
• Manufacturer: AD [Analog Devices]

CLOCK OUTPUT PHASE NOISE
Table 5.
Parameter
CLK1-TO-LVPECL ADDITIVE PHASE NOISE
CLK1 = 622.08 MHz, OUT = 622.08 MHz
CLK1 = 622.08 MHz, OUT = 155.52 MHz
CLK1 = 622.08 MHz, OUT = 38.88 MHz
CLK1 = 491.52 MHz, OUT = 61.44 MHz
CLK1 = 491.52 MHz, OUT = 245.76 MHz
CLK1 = 245.76 MHz, OUT = 61.44 MHz
Divide Ratio = 1
Divide Ratio = 4
Divide Ratio = 16
Divide Ratio = 8
Divide Ratio = 2
Divide Ratio = 4
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
Min
Rev. A | Page 9 of 60
Typ
−125
−132
−140
−148
−153
−154
−128
−140
−148
−155
−161
−161
−135
−145
−158
−165
−165
−166
−131
−142
−153
−160
−165
−165
−125
−132
−140
−151
−157
−158
−138
−144
−154
−163
−164
−165
Max
Unit
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Test Conditions/Comments
Distribution Section only; does not
include PLL or external VCO/VCXO
Input slew rate > 1 V/ns
AD9511