AD9511BCPZ-REEL AD [Analog Devices], AD9511BCPZ-REEL Datasheet - Page 49

• Manufacturer Part Number: AD9511BCPZ-REEL
• Description: 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs
• Manufacturer: AD [Analog Devices]

Reg.
Addr.
(Hex)
0A
0A
0A
0A
0A
0B
0C
0D
0D
0D
0D
0D
0E-33
Bit(s) Name
<1:0> PLL Power-Down
<4:2> Prescaler Value
<5>
<6>
<7>
<5:0> 14-Bit Reference
<7:0> 14-Bit Reference
<1:0> Antibacklash
<4:2>
<5>
<6>
<7>
(P/P+1)
B Counter Bypass Only valid when operating the prescaler in fixed divide (FD) mode. When this bit is set, the
Counter, MSBs
Counter, R LSBs
Pulse-Width
Digital Lock
Detect Window
Digital Lock
Detect Window
Lock Detect
Disable
Unused
Description
01 = Asynchronous Power-Down (Default).
<1>
0
0
1
1
<4>
0
0
0
0
1
1
1
1
DM = Dual Modulus, FD = Fixed Divide.
Not Used.
B counter is divided by 1. This allows the prescaler setting to determine the divide for the
N divider.
Not Used.
R Divider (MSB) <13:8>.
R Divider (MSB) <7:0>.
<1>
0
0
1
1
Not Used.
<5>
0 (Default)
1
If the time difference of the rising edges at the inputs to the PFD are less than the lock detect
window time, the digital lock detect flag is set. The flag remains set until the time difference is
greater than the loss-of-lock threshold.
0 = Normal Lock Detect Operation (Default).
1 = Disable Lock Detect.
Not Used.
Not Used.
Digital Lock Detect Window (ns) Digital Lock Detect Loss-of-Lock Threshold (ns)
9.5
3.5
Rev. A | Page 49 of 60
<3>
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
<2> Mode Prescaler Mode
FD
FD
DM
DM
DM
DM
DM
FD
0
1
0
1
1
0
1
<0>
<0>
0
15
7
Divide by 1
Divide by 2
2/3
4/5
8/9
16/17
32/33
Divide by 3
Antibacklash Pulse Width (ns)
1.3 (Default)
2.9
6.0
1.3
Mode
Normal Operation
Asynchronous Power-Down
Normal Operation
Synchronous Power-Down
AD9511