CY7C1470V25-167AXI CYPRESS [Cypress Semiconductor], CY7C1470V25-167AXI Datasheet - Page 20

• Manufacturer Part Number: CY7C1470V25-167AXI
• Description: 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05290 Rev. *I
Switching Waveforms
Read/Write/Timing
Notes:
21. For this waveform ZZ is tied LOW.
22. When CE is LOW, CE
23. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved).Burst operations are optional.
In-Out (DQ)
ADDRESS
ADV/LD
Data
BW
CEN
CLK
WE
OE
CE
x
t
t
t
CENS
CES
AS
[21, 22, 23]
WRITE
1
D(A1)
A1
is LOW, CE
1
t
t
CENH
t
AH
CEH
2
WRITE
D(A2)
is HIGH and CE
2
A2
t
CH
t CYC
t
DS
t
CL
D(A2+1)
BURST
WRITE
D(A1)
3
3
t
is LOW. When CE is HIGH,CE
DH
DON’T CARE
D(A2)
READ
Q(A3)
A3
4
D(A2+1)
Q(A4)
READ
A4
5
t
t
CO
CLZ
1
is HIGH or CE
UNDEFINED
Q(A4+1)
BURST
READ
Q(A3)
6
t
DOH
t
OEHZ
2
is LOW or CE
WRITE
D(A5)
Q(A4)
A5
7
t
OEV
t
OELZ
3
is HIGH.
Q(A4+1)
READ
Q(A6)
A6
8
t
t
DOH
CHZ
CY7C1470V25
CY7C1472V25
CY7C1474V25
WRITE
D(A7)
D(A5)
9
A7
Page 20 of 28
DESELECT
10
Q(A6)
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