VSC838UG VITESSE [Vitesse Semiconductor Corporation], VSC838UG Datasheet - Page 5

• Manufacturer Part Number: VSC838UG
• Description: 3.2Gb/s 36x37 Crosspoint Switch
• Manufacturer: VITESSE [Vitesse Semiconductor Corporation]

G52351-0, Rev 3.0
02/12/01
Preliminary Data Sheet
VSC838
AC Characteristics
Table 1: Data Path
NOTES: (1) Tested on a sample basis only. (2) Broadband (unfiltered) deterministic jitter added to a jitter-free input, 2
Table 2: Program Interface Timing
Parameter
f
T
T
t
t
t
t
Parameter
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
R
R
jR
jP
RATE
SKW
PDAY
sWR
sCS
sSDIN
sLOAD
sSERIAL
sSCAN
, t
, t
hWR
PWLW
hCSB
PWCFG
hSDIN
perSCLK
hLOAD
hSERIAL
dSDOUT
PWINIT
hSCAN
F
F
Maximum data rate
Channel-to-channel delay skew
Propagation Delay from an A input to a Y output
High-speed input rise/fall times, 20% to 80%
High-speed output rise/fall times, 20% to 80%
Output added delay jitter, rms
Output added delay jitter, peak-to-peak
Setup time from INCHAN[5:0] or OUTCHAN5:0] to rising edge of
WR.
Hold time from rising edge of WRB to INCHAN[5:0] or
OUTCHAN[5:0].
Pulse width (HIGH or LOW) on LOAD
Setup time from CS to falling edge of LOAD or ALE_SCN in parallel or
burst mode, or rising edge of LOAD in serial mode.
Hold time of CS rising edge after LOAD or ALE_SCN rising in parallel
or burst mode, or falling edge of LOAD in serial mode, or falling edge of
CONFIG in any mode.
Pulse width (HIGH or LOW) on CONFIG.
Setup time from INCHAN0(SDIN) to INCHAN1(SCLK) rising.
Hold time of INCHAN0(SDIN) after INCHAN1(SCLK) rising.
Minimum period of SCLK in serial mode.
Setup time from LOAD to INCHAN1(SCLK) rising.
Hold time of LOAD after INCHAN1(SCLK) rising.
Setup time from SERIAL rising to INCHAN1(SCLK) rising when
entering serial mode or SERIAL falling to LOAD falling when entering
parallel mode or SERIAL falling to LOAD rising when entering burst
mode.
Hold time from INCHAN1(SCLK) rising to SERIAL falling when
exiting serial mode.
Delay from INCHAN1(SCLK) rising to SDOUT, 20pF load.
Pulse width (HIGH or LOW) on INIT.
Setup time from ALE_SCN to INCHAN1(SCLK) rising when starting
or completing a serial read-back sequence.
Hold time of ALE_SCN after INCHAN1(SCLK) rising when starting or
completing a serial read-back sequence.
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: [phone] • Email: [e-mail]
VITESSE
SEMICONDUCTOR CORPORATION
(1, 2)
Description
Description
Internet: www.vitesse.com
(1, 2)
Min
3.35
1.45
6.75
6.75
1.65
1.85
0.95
0.90
6.75
1.65
Min
1.0
1.0
15
—
0
0
0
-
-
-
-
-
-
-
36x37 Crosspoint Switch
Typ
Typ
300
750
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-
-
-
23
-1 PRBS data pattern.
Max
Max
6.20
150
150
3.2
10
40
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-
-
Units
Units
Gb/s
3.2Gb/s
ps
ps
ps
ps
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Page 5