VSC8117QP2 VITESSE [Vitesse Semiconductor Corporation], VSC8117QP2 Datasheet - Page 3

• Manufacturer Part Number: VSC8117QP2
• Description: ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery
• Manufacturer: VITESSE [Vitesse Semiconductor Corporation]

VSC8117
G52221-0, Rev. 4.1
1/8/00
Data Sheet
Transmit Section
TXLSCKOUT also latches TXIN[7:0] into the part as shown in Figure 1. The data is then serialized (MSB lead-
ing) and presented at the TXDATAOUT+/- pins. The serial output stream is synchronized to the CMU generated
clock which is a phase locked and frequency scaled version of the input reference clock. External control inputs
CMUFREQSEL and STS-12 select the multiply ratio of the CMU for either STS-3 (155MbS) or STS-12
(622Mb/s) transmission (see Table 10). A divide-by-8 version of the CMU clock (TXLSCKOUT) should be
used to synchronize the transmit interface of the UNI device to the transmit input registers on the VSC8117.
Receive Section
inputs. The CRU recovers the high speed clock from the serial data input. The serial data is converted to byte-
wide parallel data and presented on RXOUT[7:0] pins. A divide-by-8 version of the high-speed clock
(RXLSCKOUT) should be used to synchronize the byte-serial RXOUT[7:0] data with the receive portion of the
UNI device. The on-chip CRU is by-passed by setting the DSBLCRU input high. In this mode, the serial input
data and corresponding clock are received by the RXDATAIN and RXCLKIN inputs respectively. RXDATAIN
is clocked in on the rising edge of RXCLKIN+. See Figure 2.
frame, aligns the received serial data on byte boundaries, and initiates a frame pulse on FP coincident with the
byte aligned data. The frame recovery is initiated when OOF is held high which must occur at least 4 byte clock
cycles before the A1A2 boundary. The OOF input control is a level-sensitive signal, and the VSC8117 will con-
tinually perform frame detection and recovery as long as this pin is held high even if 1 or more frames has been
detected. Frame detection and recovery occurs when a series of three A1 bytes followed by three A2 bytes has
been detected. The parallel output data on RXOUT[7:0] will be byte aligned starting on the third A2 byte. When
a frame is detected, a single byte clock period long pulse is generated on FP which is synchronized with the
byte-aligned third A2 byte on RXOUT[7:0]. The frame detector sends a FP pulse only if OOF is high.
Byte-wide data is presented to TXIN[7:0] and is clocked into the part on the rising edge of TXLSCKOUT.
High speed Non-Return to Zero (NRZ) serial data at 155Mb/s or 622Mb/s are received by the RXDATAIN
The receive section also includes frame detection and recovery circuitry which detects the SONET/SDH
TXDATAOUT+
TXDATAOUT-
REFCLK
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]
Figure 1: Data and Clock Transmit Block Diagram
VITESSE
VITESSE SEMICONDUCTOR CORPORATION
SEMICONDUCTOR CORPORATION
CMU
Q
VSC8117
ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux
D
with Integrated Clock Generation and Clock Recovery
Divide-by-8
Q
D
TXIN[7:0]
TXLSCKIN
TXLSCKOUT
PM5355
Q
D
Page 3