VSC8115YA1 VITESSE [Vitesse Semiconductor Corporation], VSC8115YA1 Datasheet - Page 6

• Manufacturer Part Number: VSC8115YA1
• Description: STS-12/STS-3 Multi Rate Clock and Data Recovery Unit
• Manufacturer: VITESSE [Vitesse Semiconductor Corporation]

STS-12/STS-3 Multi Rate
Clock and Data Recovery Unit
Page 6
Retimed Data and Clock Outputs AC Specification
the clock output. Data valid time is larger for OC-3/STS-3 mode of operation than that of OC-12/STS-12. Data
valid time before the output clock’s rising edge is the available setup time (t
the clock’s rising edge is the available hold time (t
Table 3: Retimed Data and Clock Outputs Timing
High Speed Outputs
LVPECL outputs. If used as LVDS outputs, the transmission lines should be routed with 100-ohm differential
impedance, and they need to be terminated at the receive end with a 100-ohm resistor across the differential
pair. If used as LVPECL outputs, the transmission line should be 50-ohm terminated with 50-ohm pull down
resistors near the receiving end.
Parameters
As indicated in figure 3, it is recommended that the retimed data output be captured with the rising edge of
The high speed output buffers, DATAOUT+/- and CLKOUT+/-, can be terminated as either LVDS or
t
t
su
h
DATAOUT+/-
CLKOUT+
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Figure 3: Retimed Data and Clock Outputs Timing Diagram
Minimum Available Setup Time
Minimum Available Hold Time
Description
t
VITESSE
su
VITESSE SEMICONDUCTOR CORPORATION
SEMICONDUCTOR CORPORATION
t
h
h
).
STS-12 Operation
(622.08MHz)
450 pS
650 pS
su
) while the data valid time after
Target Specification
STS-3 Operation
(155.52MHz)
2.0 nS
3.0 nS
VSC8115
G52272-0, Rev. 1.1
9/29/00