VSC8113QB1 VITESSE [Vitesse Semiconductor Corporation], VSC8113QB1 Datasheet - Page 24

• Manufacturer Part Number: VSC8113QB1
• Description: ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery
• Manufacturer: VITESSE [Vitesse Semiconductor Corporation]

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
Page 24
Application Notes
Interconnecting the Byte Clocks (TXLSCKOUT and TXLSCKIN)
much flexibility in system-level clocking schemes as possible. Since the byte clock (TXLSCKOUT) clocks both
the VSC8113 and the UNI devices, it is important to pay close attention to the routing of this signal. The UNI
device in general is a CMOS part which can have very wide spreads in timing (1-11ns clock in to parallel data
out for the PM5355), which utilizes most of the 12.86ns period (at 78MHz), leaving little for the trace delays
and set-up times required to interconnect the 2 devices.
setup and hold time margin at the inputs of the VSC8113. Figure 12 suggests two different ways of routing the
TXLSCKOUT-to-TXLSCKIN clock trace when used in a 622 MHz mode, which ever method is used the trans-
mission line trace impedance should be no lower than 75 ohms.
hold time margin for the TXIN input of
byte data. This interface provides a setup and hold time margin for the TXIN input of
to be less than 0.43ns (~3 inches).
other as possible. If the one-way trace delay cannot be kept less than 0.43ns with a 50 pf load, daisy-chaining
(option 2) should be applied - close attention must be paid to signal routing in this case because of the lack of
hold time margin.
• T
Option (2) does not provide any hold time margin, while option (1) requires the one-way trace delay (T
The general recommendation is to apply option (1) and place the VSC8113 and PM5355 as close to each
The byte clock (TXLSCKOUT and TXLSCKIN) on the VSC8113 has been brought off-chip to allow as
The VSC8113 and the UNI device should be placed as close to each other as possible to provide maximum
(1) TXLSCKOUT and TXLSCKIN are tied together at the pins of the VSC8113. This provides a setup and
• T
• T
(2) TXLSCKOUT is daisy chained to the UNI device and then routed back to the VSC8113 along with the
• T
hold,margin
hold,margin
su,margin
su,margin
= T
= T
= T
= T
clk
clk
TCLK-POUT,min
TCLK-POUT,min
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]
- T
- T
TXLSCKOUT
TXLSCKIN
TCLK-POUT,max
TCLK-POUT,max
TXIN[7:0]
VSC8113
Figure 12: Interconnecting the Byte Clocks
VITESSE
VITESSE SEMICONDUCTOR CORPORATION
SEMICONDUCTOR CORPORATION
(PM5355) - T
(PM5355) - T
(PM5355) - T
(PM5355) - T
(1)
hold,min
hold,min
T
su,min
su,min
trace
(VSC8113) + 2xT
(VSC8113) = 0ns
(VSC8113) - 2xT
(VSC8113) = 0.86ns
(2)
trace
PM5355
POUT[7:0]
TCLK
trace
= 2xT
= 0.86ns - 2xT
trace
VSC8113
trace
Data Sheet
G52154-0, Rev 4.2
trace
3/19/99
)