VSC8021FC VITESSE [Vitesse Semiconductor Corporation], VSC8021FC Datasheet - Page 3

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VSC8021FC

Manufacturer Part Number
VSC8021FC
Description
2.5Gb/s SONET-Compatible 8-Bit MUX/DEMUX Chipset
Manufacturer
VITESSE [Vitesse Semiconductor Corporation]
Datasheet
Data Sheet
VSC8021/VSC8022
G52028-0, Rev 4.1
05/25/01
VSC8022
accepts a serial data input ( DI, DIN ) at rates up to 2.5Gb/s and converts it into 8 parallel differential ECL data outputs
( D1-D8, D1N-D8N ) at rates up to 312.5Mb/s. Valid parallel data outputs are indicated by the divide by 8 differential
clock outputs BYCKO, BYCKON .
ing edge on the OOFN ECL input when the FDIS input is low. Once enabled, the frame recovery circuit starts look-
ing for the SONET framing sequence. Once the frame is detected, the word boundary is realigned, a confirmation
signal is sent off-chip through the FP ECL output and the frame recovery circuits are disabled. While the frame
aligner is hunting for the frame, BYCKO, BYCKON and parallel data are invalid.
input while FDIS is high.
The VSC8022 contains both a 1:8 demultiplexer and SONET frame recovery circuitry. The 1:8 demultiplexer
The VSC8022 also contains a SONET frame recovery circuit. The frame recovery circuits are enabled by a fall-
Frame recovery circuits are disabled by frame detection (resulting in FP) or by a falling edge on the OOFN
Frame Recovery Disable —
Frame Recovery Clock —
Clock Inputs
High Speed
Serial Data In
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
OOFN
CLKIN
FDIS
CLKI
VITESSE
DIN
SEMICONDUCTOR CORPORATION
DI
Figure 2: VSC8022 Block Diagram
Internet: www.vitesse.com
Generator
Timing
Demultiplexer
1:8
Detection &
Recovery
SONET
Frame
2.5Gb/s SONET-Compatible
8-Bit MUX/DEMUX Chipset
FP
D8
D8N
D1
D1N
BYCKO
BYCKON
— Frame Detection Signal
Parallel
Data Outputs
Byte Clock Out
Page 3

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