CY7C1380D CYPRESS [Cypress Semiconductor], CY7C1380D Datasheet - Page 22

• Manufacturer Part Number: CY7C1380D
• Description: 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05543 Rev. *A
Switching Waveforms
Write Cycle Timing
Data Out (Q)
Data In (D)
ADDRESS
ADSC
ADSP
BWE,
ADV
BW
CLK
GW
OE
CE
X
BURST READ
High-Z
t ADS
[26, 27]
t CES
t AS
A1
t ADH
t CEH
t AH
t CH
t
OEHZ
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t CYC
t ADS
(continued)
t CL
t DS
Single WRITE
D(A1)
t ADH
t DH
A2
D(A2)
PRELIMINARY
DON’T CARE
t WES
D(A2 + 1)
BURST WRITE
t WEH
UNDEFINED
D(A2 + 1)
ADV suspends burst
D(A2 + 2)
ADSC extends burst
D(A2 + 3)
t ADS
A3
D(A3)
t ADH
t
ADVS
t WES
CY7C1380D
CY7C1382D
Extended BURST WRITE
D(A3 + 1)
t WEH
t
ADVH
Page 22 of 29
D(A3 + 2)