CY7C1363C CYPRESS [Cypress Semiconductor], CY7C1363C Datasheet
CY7C1363C
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CY7C1363C Summary of contents
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... A version of TQFP ( 3 Chip Enable Option) and 165 fBGA package only. 119 BGA is offered only in 2 Chip Enable. 3 Cypress Semiconductor Corporation Document #: 38-05541 Rev. *A PRELIMINARY Functional Description The CY7C1361C/CY7C1363C is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flowthrough SRAMs, respectively designed to interface with high-speed microprocessors with minimum ) glue logic. Maximum access delay from clock rise is 6 (133-MHz version) ...
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... BW B BYTE WRITE REGISTER DQ DQP , BYTE BWE WRITE REGISTER GW ENABLE CE1 REGISTER CE2 CE3 OE SLEEP ZZ CONTROL 1 Logic Block Diagram – CY7C1363C (512K x 18) ADDRESS A0,A1,A REGISTER MODE ADV CLK ADSC ADSP DQ ,DQP B WRITE REGISTER ,DQP WRITE REGISTER BWE GW ENABLE ...
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... SSQ SSQ DDQ DDQ DQP NC A CY7C1361C CY7C1363C CY7C1363C 15 16 (512K x 18 DDQ 76 V SSQ DQP A 73 ...
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... DDQ V 76 SSQ NC 75 DQP SSQ V 70 DDQ CY7C1363C (512K x 18 DDQ 60 V SSQ SSQ V 54 ...
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... BWE DQP MODE TMS TDI TCK CY7C1363C (512K x 18 ADSP CE A ADSC ADV ...
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... 18M SS TDI TMS CY7C1363C (512K x 18 CLK ...
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... Selects Burst Order. When tied to GND selects linear burst sequence. When tied left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up. Power supply inputs to the core of the device. Ground for the core of the device. CY7C1361C CY7C1363C Description [ and CE 1 ...
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... This pin is not available on TQFP packages Connects. Not internally connected to the die. 18M, 36M, 72M, 144M and 288M are address expansion pins are not internally connected to the die. This pin can be connected to Ground or should be left floating. CY7C1361C CY7C1363C Description through a pull DD . This pin DD ...
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... Maximum access delay from the clock rise ( 6.5 ns (133-MHz device). CDV The CY7C1361C/CY7C1363C supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium processors. The linear burst sequence is suited for processors that utilize a linear burst sequence ...
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... CY7C1361C CY7C1363C Min. Max. Unit CYC 2t ns CYC 2t ns CYC 0 ns ADV WRITE OE CLK L-H three-state L-H three-state L-H three-state ...
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... Write Bytes ( DQP , DQP , DQP D C Write Bytes ( DQP , DQP , DQP D B Write All Bytes Write All Bytes Truth Table for Read/Write [3, 8] Function (CY7C1363C) Read Read Write Byte A – and DQP ) A A Write Byte B – and DQP ) B B Write All Bytes ...
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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1361C/CY7C1363C incorporates a serial boundary scan test access port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This part operates in accordance with IEEE Standard 1149.1-1900, but doesn’t have the set of functions required for full 1149.1 compliance ...
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... SAMPLE / PRELOAD instruction. If this is an issue still possible to capture all other signals PRELOAD portion of and simply ignore the value of the CK and CK# captured in the boundary scan register. CY7C1361C CY7C1363C instructions. Unlike the SAMPLE/PRELOAD and t ). The SRAM clock input might not be CS ...
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... Do not use these instructions CYC TL t TMSS t TMSH t TDIS t TDIH DON’T CARE [9, 10] Over the Operating Range Parameter / ns CY7C1361C CY7C1363C TDOV t TDOX UNDEFINED Min. Max Page ...
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... OL GND < V < DDQ CY7C1361C CY7C1363C (256K x36) (512K x18) 000 000 01011 01011 000001 000001 100110 010110 00000110100 00000110100 1 1 CY7C1361C CY7C1363C ......................................... V 1.25V 50 TDO 20pF O (0°C < TA < +70° 3.3V ±0.165V unless DD Conditions Min 3.3V 2.4 DDQ V = 2.5V 2.0 DDQ V = 3.3V 2 ...
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... RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Document #: 38-05541 Rev. *A PRELIMINARY CY7C1361C CY7C1363C Description Page ...
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... A 28 Internal Internal Internal 35 36 CY7C1361C CY7C1363C CY7C1363C (512K x 18) Signal Name BIT# BALL ID CLK BWE ADSC ADSP ADV 43 R3 ...
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... CY7C1361C CY7C1363C CY7C1363C (512K x 18) Signal Name BIT# BALL ID B6 CLK BWE ADSC ADSP ADV 43 R1 B10 ...
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... inputs static /2), undershoot: V (AC) > -2V (Pulse width less than t CYC IL (min.) within 200ms. During this time V < CY7C1361C CY7C1363C Ambient Temperature V DD 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5% –40°C to +85°C Min. Max. 3.135 3.6 3.135 ...
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... SCOPE ( 1667Ω 2.5V OUTPUT =1538Ω INCLUDING JIG AND (b) SCOPE [20, 21] 133 MHz Min. Max. [16] 1 7.5 3.0 3.0 6.5 2.0 0 3.5 3.5 [17, 18, 19] 0 CY7C1361C CY7C1363C TQFP BGA fBGA Package Package Package TQFP BGA fBGA Package Package Package ...
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... V POWER is less than t and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ = 3.3V and is 1.25V when V = 2.5V. DDQ CY7C1361C CY7C1363C 117 MHz 100 MHz Min. Max. Min. Max. 3.5 3.5 1.5 1.5 1.5 1.5 1 ...
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... WEH t t ADVH ADVS t CDV t OELZ t OEHZ t DOH Q(A2) Q( DON’T CARE is HIGH and CE is LOW. When CE is HIGH CY7C1361C CY7C1363C ADV suspends burst Q( Q( Q(A2) Q( Burst wraps around to its initial state BURST READ UNDEFINED is HIGH LOW HIGH Deselect Cycle ...
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... Full width write can be initiated by either GW LOW HIGH, BWE LOW and BW Document #: 38-05541 Rev. *A PRELIMINARY ADSC extends burst WES WEH ADV suspends burst D(A2 BURST WRITE DON’T CARE UNDEFINED LOW. X CY7C1361C CY7C1363C t ADS t ADH A3 t WES t WEH t ADVS t ADVH D( D(A3 Extended BURST WRITE Page ...
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... Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 27. DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05541 Rev. *A PRELIMINARY WEH WES OELZ D(A3) t OEHZ t CDV Q(A4) Single WRITE DON’T CARE CY7C1361C CY7C1363C A5 D(A5) Q(A4+1) Q(A4+2) Q(A4+3) BURST READ Back-to-Back UNDEFINED A6 D(A6) WRITEs Page ...
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... Ordering Code 133 CY7C1361C-133AXC CY7C1363C-133AXC CY7C1361C-133AXI CY7C1363C-133AXI CY7C1361C-133AJXC CY7C1363C-133AJXC CY7C1361C-133AJXI CY7C1363C-133AJXI CY7C1361C-133BGC CY7C1363C-133BGC CY7C1361C-133BGI CY7C1363C-133BGI CY7C1361C-133BZC CY7C1363C-133BZC CY7C1361C-133BZI CY7C1363C-133BZI Document #: 38-05541 Rev. *A PRELIMINARY ZZI I DDZZ High-Z DON’T CARE Package Name Part and Package Type A101 100-lead Thin Quad Flat Pack ( 1.4 mm) ...
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... CY7C1361C-100AXC CY7C1363C-100AXC CY7C1361C-100AXI CY7C1363C-100AXI CY7C1361C-100AJXC CY7C1363C-100AJXC CY7C1361C-100AJXI CY7C1363C-100AJXI CY7C1361C-100BGC CY7C1363C-100BGC CY7C1361C-100BGI CY7C1363C-100BGI CY7C1361C-100BZC CY7C1363C-100BGC CY7C1361C-100BZI CY7C1363C-100BGI Shaded areas contain advance information. Please contact your local sales representative for availability of these parts.Lead-free BG and BZ packages (Ordering code:BGX,BZX) will be available in 2005. Document #: 38-05541 Rev. *A ...
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... GAUGE PLANE R 0.08 MIN. 0°-7° 0.20 MAX. 0.60±0.15 0.20 MIN. 1.00 REF. DETAIL Document #: 38-05541 Rev. *A PRELIMINARY DIMENSIONS ARE IN MILLIMETERS. 16.00±0.20 14.00±0. 0.30±0.08 0.65 TYP STAND-OFF 0.05 MIN. SEATING PLANE 0.15 MAX. A CY7C1361C CY7C1363C 1.40±0.05 12°±1° A SEE DETAIL (8X) 0.20 MAX. 1.60 MAX. 51-85050-*A Page ...
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... Package Diagrams (continued) Document #: 38-05541 Rev. *A PRELIMINARY 119-Lead PBGA ( 2.4 mm) BG119 CY7C1361C CY7C1363C 51-85115-*B Page ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY 165 FBGA 1.40 mm BB165D CY7C1361C CY7C1363C 51-85180-** Page ...
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... Document History Page Document Title: CY7C1361C/CY7C1363C 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM (Preliminary) Document Number: 38-05541 REV. ECN NO. Issue Date ** 241690 See ECN *A 278969 See ECN Document #: 38-05541 Rev. *A PRELIMINARY Orig. of Change RKF New data sheet RKF Changed Boundary Scan order to match the B rev of these devices. ...