M29W400B STMICROELECTRONICS [STMicroelectronics], M29W400B Datasheet - Page 12

• Manufacturer Part Number: M29W400B
• Description: 4 Mbit 512Kb x8 or 256Kb x16, Boot Block Low Voltage Single Supply Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M29W400T, M29W400B
Table 10. Polling and Toggle Bits
Note: 1. Toggle if the address is within a block being erased.
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Toggle Bit (DQ6). When Programming or Erasing
operations are in progress, successive attempts to
read DQ6 will output complementary data. DQ6 will
toggle following toggling of either G, or E when G
is low. The operation is completed when two suc-
cessive reads yield the same output data. The next
read will output the bit last programmedor a ’1’after
erasing. The toggle bit DQ6 is valid only during
P/E.C. operations, that is after the fourth W pulse
for programming or after the sixth W pulse for
Erase. If the blocks selected for erasure are pro-
tected, DQ6 will toggle for about 100 s and then
return back to Read. DQ6 will be set to ’1’ if a Read
operation is attempted on an Erase Suspendblock.
When erase is suspended DQ6 will toggle during
programming operations in a block different to the
block in Erase Suspend. Either E or G toggling will
cause DQ6 to toggle. See Figure 12 for Toggle Bit
flowchart and Figure 13 for Toggle Bit waveforms.
Toggle Bit (DQ2). This toggle bit, together with
DQ6, can be used to determine the device status
during the Erase operations.It can also be used to
identify the block being erased. During Erase or
Erase Suspend a read from a block being erased
will cause DQ2 to toggle. A read from a block not
being erased will set DQ2 to ’1’ during erase and
to DQ2 during Erase Suspend. During Chip Erase
a read operation will cause DQ2 to toggle as all
blocks are being erased. DQ2 will be set to ’1’
during program operation and when erase is com-
plete. After erase completion and if the error bit
DQ5 is set to ’1’, DQ2 will toggle if the faulty block
is addressed.
Error Bit (DQ5). This bit is set to ’1’ by the P/E.C.
when there is a failure of programming, block
erase, or chip erase that results in invalid data in
the memory block. In caseof an errorin block erase
or program, the block in which the error occured or
to which the programmed data belongs, must be
discarded. The DQ5 failure condition will also ap-
Program
Erase
Erase Suspend Read
(in Erase Suspend
block)
Erase Suspend Read
(outside Erase Suspend
block)
Erase Suspend Program
’1’ if the address is within a block not being erased.
Mode
DQ7
DQ7
DQ7
DQ7
0
1
Toggle
Toggle
Toggle
DQ6
DQ6
1
Note 1
Toggle
DQ2
DQ2
N/A
1
pear if a user tries to program a ’1’ to a location that
is previously programmed to ’0’. Other Blocks may
stillbe used. The errorbit resets after a Read/Reset
(RD) instruction. In case of success of Program or
Erase, the error bit will be set to ’0’ .
Erase Timer Bit (DQ3). This bit is set to ’0’ by the
P/E.C. when the last block Erase command has
been entered to the Command Interface and it is
awaiting the Erase start. When the erase timeout
period is finished, after 50 s to 90 s, DQ3 returns
to ’1’.
Coded Cycles
The two Coded cycles unlock the Command Inter-
face. They are followed by an input command or a
confirmation command. The Coded cycles consist
of writing the data AAh at address AAAAh in the
Byte-wide configuration and at address 5555h in
the Word-wide configuration during the first cycle.
During the second cycle the Coded cycles consist
of writing the data 55h at address 5555h in the
Byte-wide configuration and at address 2AAAh in
the Word-wide configuration.In the Byte-wide con-
figurationthe address lines A–1 to A14 are valid, in
Word-wide A0 to A14 are valid, other address lines
are ’don’t care’. The Coded cycles happen on first
and second cycles of the command write or on the
fourth and fifth cycles.
Instructions
See Table 8.
Read/Reset (RD) Instruction. The Read/Reset
instruction consists of one write cycle giving the
command F0h. It can be optionallyprecededby the
two Coded cycles. Subsequentread operationswill
read the memory array addressed and output the
data read. A wait state of 10 s is necessary after
Read/Reset prior to any valid read if the memory
was in an Erase mode when the RD instruction is
given.
Auto Select (AS) Instruction. This instruction
uses the two Coded cycles followed by one write
cycle giving the command 90h to address AAAAh
in the Byte-wide configuration or address 5555h in
the Word-wide configuration for command set-up.
A subsequent read will output the manufacturer
code and the device code or the block protection
status depending on the levels of A0 and A1. The
manufacturer code, 20h, is output when the ad-
dresses lines A0 and A1 are Low, the device code,
EEh for Top Boot, EFh for Bottom Boot is output
when A0 is High with A1 Low.
The AS instruction also allows access to the block
protectionstatus.Aftergiving the AS instruction, A0
is set to V
the address of the block to be verified. A read in
these conditions will output a 01h if the block is
protected and a 00h if the block is not protected.
IL
with A1 at V
IH
, while A12-A17 define