CY7C1361B CYPRESS [Cypress Semiconductor], CY7C1361B Datasheet - Page 26

• Manufacturer Part Number: CY7C1361B
• Description: 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05302 Rev. *B
Timing Diagrams
Read Cycle Timing
Note:
21. On this diagram, when CE is LOW: CE
GW, BWE,BW
Data Out (Q)
ADDRESS
CLK
ADSP
ADSC
ADV
OE
X
CE
High-Z
[21]
t ADS
t AS
t CES
A1
t ADH
t CLZ
t AH
t CEH
t
t OEV
CH
t CDV
t CYC
Single READ
t
t CL
WES
1
Q(A1)
is LOW, CE
t
WEH
t OEHZ
t ADS
A2
2
t ADH
is HIGH and CE
t OELZ
t
ADVS
Q(A2)
t
t DOH
ADVH
t CDV
3
is LOW. When CE is HIGH: CE
Q(A2 + 1)
DON’T CARE
Q(A2 + 2)
ADV suspends burst
UNDEFINED
BURST
READ
1
is HIGH or CE
Q(A2 + 3)
2
is LOW or CE
Q(A2)
Burst wraps around
to its initial state
CY7C1361B
CY7C1363B
3
Q(A2 + 1)
is HIGH.
Page 26 of 34
Deselect Cycle
Q(A2 + 2)
t CHZ