CY7C1361A CYPRESS [Cypress Semiconductor], CY7C1361A Datasheet - Page 9

• Manufacturer Part Number: CY7C1361A
• Description: 256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05259 Rev. *A
Partial Truth Table for Read/Write
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
ZZ Mode Electrical Characteristics
IEEE 1149.1 Serial Boundary Scan (JTAG)
Overview
This device incorporates a serial boundary scan test access
port (TAP). This port is designed to operate in a manner
consistent with IEEE Standard 1149.1-1990 (commonly
referred to as JTAG), but does not implement all of the
functions required for IEEE 1149.1 compliance. Certain
functions have been modified or eliminated because their
implementation places extra delays in the critical speed path
of the device. Nevertheless, the device supports the standard
TAP controller architecture (the TAP controller is the state
machine that controls the TAPs operation) and can be
expected to function in a manner that does not conflict with the
operation of devices with IEEE Standard 1149.1 compliant
TAPs. The TAP operates using LVTTL/ LVCMOS logic level
signaling.
Disabling the JTAG Feature
It is possible to use this device without using the JTAG feature.
To disable the TAP controller without interfering with normal
operation of the device, TCK should be tied LOW (V
prevent clocking the device. TDI and TMS are internally pulled
up and may be unconnected. They may alternately be pulled
up to V
Upon power-up the device will come up in a reset state which
will not interfere with the operation of the device.
Test Access Port
TCK–Test Clock (INPUT)
Clocks all TAP events. All inputs are captured on the rising
edge of TCK and all outputs propagate from the falling edge
of TCK.
Note:
10. For the X18 product, there are only BWa and BWb.
Read
Read
Write one byte
Write all bytes
Write all bytes
I
t
t
DDZZ
ZZS
ZZREC
Parameter
CC
through a resistor. TDO should be left unconnected.
Function
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
Description
[10]
GW
H
H
H
H
L
SS
BWE
) to
H
X
L
L
L
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs
for the duration of t
TMS–Test Mode Select (INPUT)
The TMS input is sampled on the rising edge of TCK. This is
the command input for the TAP controller state machine. It is
allowable to leave this pin unconnected if the TAP is not used.
The pin is pulled up internally, resulting in a logic HIGH level.
TDI–Test Data In (INPUT)
The TDI input is sampled on the rising edge of TCK. This is the
input side of the serial registers placed between TDI and TDO.
The register placed between TDI and TDO is determined by
the state of the TAP controller state machine and the
instruction that is currently loaded in the TAP instruction
register (refer to Figure 1, TAP Controller State Diagram). It is
allowable to leave this pin unconnected if it is not used in an
application. The pin is pulled up internally, resulting in a logic
HIGH level. TDI is connected to the Most Significant Bit (MSB)
of any register (see Figure 2).
TDO–Test Data Out (OUTPUT)
The TDO output pin is used to serially clock data-out from the
registers. The output that is active depending on the state of
the TAP state machine (refer to Figure 1, TAP Controller State
Diagram). Output changes in response to the falling edge of
TCK. This is the output side of the serial registers placed
between TDI and TDO. TDO is connected to the Least Signif-
icant Bit (LSB) of any register (see Figure 2).
Performing a TAP Reset
The TAP circuitry does not have a reset pin (TRST, which is
optional in the IEEE 1149.1 specification). A RESET can be
performed for the TAP controller by forcing TMS HIGH (V
for five rising edges of TCK and pre-loads the instruction
register with the IDCODE command. This type of reset does
not affect the operation of the system logic. The reset affects
test logic only.
At power-up, the TAP is reset internally to ensure that TDO is
in a High-Z state.
BWa
X
H
X
L
L
Test Conditions
ZZ > V
ZZ > V
ZZ < 0.2V
DD
DD
– 0.2V
– 0.2V
ZZREC
BWb
,
H
H
X
X
ADSP, and ADSC must remain inactive
L
after the ZZ input returns LOW.
Min.
2t
CYC
BWc
H
H
X
X
L
CY7C1361A
CY7C1363A
Max.
2t
10
CYC
Page 9 of 26
BWd
X
H
H
X
L
Unit
mA
ns
ns
CC
)