CY7C1360C CYPRESS [Cypress Semiconductor], CY7C1360C Datasheet
CY7C1360C
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CY7C1360C Summary of contents
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... Offered in Lead-Free 100-pin TQFP, 119-ball BGA and 165-Ball fBGA packages • TQFP Available with 3-Chip Enable and 2-Chip Enable • IEEE 1149.1 JTAG-Compatible Boundary Scan • “ZZ” Sleep Mode Option Logic Block Diagram – CY7C1360C (256K x 36) A0, A1, A ADDRESS REGISTER MODE ...
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... Document #: 38-05540 Rev. *C PRELIMINARY A[1: BURST LOGIC Q0 DQ DQP B, B WRITE DRIVER MEMORY DQ DQP A, A WRITE DRIVER PIPELINED ENABLE 250 MHz 2.8 250 30 CY7C1360C CY7C1362C OUTPUT OUTPUT SENSE BUFFERS AMPS REGISTERS ARRAY E 200 MHz 166 MHz 3.0 3.5 220 180 30 30 DQs DQP A DQP B INPUT REGISTERS ...
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... DQP SSQ SSQ DDQ DDQ DQP CY7C1360C CY7C1362C CY7C1362C 15 16 (512K x 18 ...
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... A DQP SSQ 26 SSQ DDQ DDQ DQP CY7C1360C CY7C1362C DDQ V 76 SSQ DQP SSQ 70 V DDQ ...
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... DDQ DDQ NC/72M V U DDQ Document #: 38-05540 Rev. *C PRELIMINARY 119-ball BGA (2 Chip Enables with JTAG) CY7C1360C (256K x 36 ADSP CE A ADSC DQP ...
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... DDQ DDQ N DQP DDQ 72M A R MODE NC / 36M A Document #: 38-05540 Rev. *C PRELIMINARY 165-ball fBGA (3 Chip Enable with JTAG) CY7C1360C (256K x 36 CLK ...
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... This is a strap pin and should remain static during device operation. Mode pin has an internal pull-up. Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is not being utilized, this pin should be disconnected. This pin is not available on TQFP packages. CY7C1360C CY7C1362C Description [ ...
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... Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed ) inputs. A Global Write Write mechanism has been provided to simplify the Write operations. Because the CY7C1360C/CY7C1362C is a common I/O [2] device, the Output Enable (OE) must be deasserted HIGH , and an ...
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... Because the CY7C1360C/CY7C1362C is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQs inputs. Doing so will three-state the output drivers safety precaution, DQs are automatically three-stated whenever a Write cycle is detected, regardless of the state of OE. Burst Sequences ...
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... Current READ Cycle, Suspend Burst Current READ Cycle, Suspend Burst Current WRITE Cycle, Suspend Burst Current WRITE Cycle, Suspend Burst Current Partial Truth Table for Read/Write Function (CY7C1360C) Read Read Write Byte A – (DQ and DQP ) A A Write Byte B – (DQ and DQP ...
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... Write All Bytes Write All Bytes IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1360C/CY7C1362C incorporates a serial boundary scan test access port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This part operates in accordance with IEEE Standard 1149.1-1900, but doesn’ ...
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... The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. CY7C1360C CY7C1362C or INTEST or ...
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... These instructions are not implemented but are reserved for future use. Do not use these instructions CYC TL t TMSS t TMSH t TDIS t TDIH DON’T CARE CY7C1360C CY7C1362C and t ). The SRAM clock input might not TDOV t TDOX UNDEFINED Page ...
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... V = 3.3V OH DDQ I = –1 2.5V OH DDQ I = –100 µ 3.3V OH DDQ V = 2.5V DDQ 3.3V OL DDQ 2.5V OL DDQ /t = 1ns CY7C1360C CY7C1362C Min. Max. Unit MHz ........................................... V to 2.5V SS 1.25V 50W Z = 50W 20pF O Min ...
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... Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. CY7C1360C CY7C1362C [12] Min. Max. = 3.3V ...
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... R = 317Ω 3.3V OUTPUT 351Ω INCLUDING JIG AND (b) SCOPE R = 1667Ω 2.5V OUTPUT =1538Ω INCLUDING JIG AND (b) SCOPE CY7C1360C CY7C1362C ALL INPUT PULSES V DDQ 90% 10% GND ≤ (c) ALL INPUT PULSES V DDQ 90% 10% GND ≤ (c) Page ...
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... Boundary Scan Order CY7C1360C (256K x 36) Signal Bit# Ball ID Name Bit CLK BWE ADSC ADSP ADV 43 8 B10 A10 C11 DQP E10 F10 ...
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... BGA Boundary Scan Order CY7C1360C (256K x 36) Signal Bit# Ball ID Name BIT# BALL ID 1 CLK BWE ADSC ADSP ADV DQP ...
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... /2), undershoot: V (AC) > –2V (Pulse width less than t CYC IL (min.) within 200 ms. During this time V < CY7C1360C CY7C1362C Ambient Temperature V DD 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5% –40°C to +85°C Min. Max. 3.135 3.135 V 2.375 2 ...
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... SCOPE R = 1667Ω 2.5V OUTPUT =1538Ω INCLUDING JIG AND SCOPE (b) [17, 18] 250 MHz Min. [19] 1 4.0 1.8 1.8 1.25 = 3.3V and is 1.25V when V = 2.5V. DDQ CY7C1360C CY7C1362C 100 TQFP 119 BGA 165 fBGA Package Package Package 29.41 34.1 16.8 6.13 14.0 100 TQFP 119 BGA 165 fBGA Package Package Package ...
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... V POWER is less than t and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ CY7C1360C CY7C1362C 200 MHz 166 MHz Max Min. Max Min. 1.25 1.25 2.8 1.25 3.0 1.25 2.8 3 2.8 3.0 1.5 1.5 1 ...
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... OEV OEHZ t OELZ t DOH Q(A2) Q( Q(A1) DON’T CARE UNDEFINED is HIGH and CE is LOW. When CE is HIGH CY7C1360C CY7C1362C A3 Burst continued with new base address Deselect cycle t CHZ Q( Q( Q(A2) Q( Burst wraps around to its initial state BURST READ is HIGH LOW HIGH ...
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... Full width Write can be initiated by either GW LOW HIGH, BWE LOW and BW Document #: 38-05540 Rev. *C PRELIMINARY A2 t WES t WEH ADV suspends burst D(A2 BURST WRITE DON’T CARE UNDEFINED LOW. X CY7C1360C CY7C1362C ADSC extends burst t ADS t ADH A3 t WES t WEH t t ADVH ADVS D( D( D(A3) ...
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... The data bus (Q) remains in high-Z following a Write cycle, unless a new Read access is initiated by ADSP or ADSC. 26 HIGH. Document #: 38-05540 Rev. *C PRELIMINARY WES t WEH OELZ D(A3) t OEHZ Q(A2) Single WRITE DON’T CARE UNDEFINED CY7C1360C CY7C1362C A5 D(A5) Q(A4) Q(A4+1) Q(A4+2) Q(A4+3) BURST READ A6 D(A6) Back-to-Back WRITEs Page ...
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... CY7C1362C-250BGC CY7C1360C-250BGI CY7C1362C-250BGI CY7C1360C-250BZC CY7C1362C-250BZC CY7C1360C-250BZI CY7C1362C-250BZI CY7C1360C-250BGXC CY7C1362C-250BGXC CY7C1360C-250BGXI CY7C1362C-250BGXI CY7C1360C-250BZXC CY7C1362C-250BZXC CY7C1360C-250BZXI CY7C1362C-250BZXI Notes: 27. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 28. DQs are in High-Z when exiting ZZ sleep mode. ...
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... CY7C1362C-200AJXC CY7C1360C-200AJXI CY7C1362C-200AJXI CY7C1360C-200BGC CY7C1362C-200BGC CY7C1360C-200BGI CY7C1362C-200BGI CY7C1360C-200BZC CY7C1362C-200BZC CY7C1360C-200BZI CY7C1362C-200BZI CY7C1360C-200BGXC CY7C1362C-200BGXC CY7C1360C-200BGXI CY7C1362C-200BGXI CY7C1360C-200BZXC CY7C1362C-200BZXC CY7C1360C-200BZXI CY7C1362C-200BZXI Document #: 38-05540 Rev. *C PRELIMINARY Package Name Part and Package Type A101 Lead-Free 100-lead Thin Quad Flat Pack ( 1.4mm) 3 Chip Enables A101 Lead-Free 100-lead Thin Quad Flat Pack ( ...
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... CY7C1362C-166AJXI CY7C1360C-166BGC CY7C1362C-166BGC CY7C1360C-166BGI ICY7C1362C-166BGI CY7C1360C-166BZC CY7C1362C-166BZC CY7C1360C-166BZI ICY7C1362C-166BZI CY7C1360C-166BGXC CY7C1362C-166BGXC CY7C1360C-166BGXI ICY7C1362C-166BGXI CY7C1360C-166BZXC CY7C1362C-166BZXC CY7C1360C-166BZXI CY7C1362C-166BZXI Shaded areas contain advance information. Please contact your local sales representative for availability of these parts. Document #: 38-05540 Rev. *C PRELIMINARY Package Name Part and Package Type A101 Lead-Free 100-lead Thin Quad Flat Pack ( ...
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... GAUGE PLANE R 0.08 MIN. 0°-7° 0.20 MAX. 0.60±0.15 0.20 MIN. 1.00 REF. DETAIL Document #: 38-05540 Rev. *C PRELIMINARY DIMENSIONS ARE IN MILLIMETERS. 16.00±0.20 14.00±0. 0.30±0.08 0.65 TYP STAND-OFF 0.05 MIN. SEATING PLANE 0.15 MAX. A CY7C1360C CY7C1362C 1.40±0.05 12°±1° A SEE DETAIL (8X) 0.20 MAX. 1.60 MAX. 51-85050-*A Page ...
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... Package Diagrams (continued) Document #: 38-05540 Rev. *C PRELIMINARY 119-Lead PBGA ( 2.4 mm) BG119 CY7C1360C CY7C1362C 51-85115-*B Page ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PRELIMINARY 165 FBGA 1.40 MM BB165D CY7C1360C CY7C1362C 51-85180-** Page ...
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... Document History Page Document Title: CY7C1360C/CY7C1362C 9-Mbit (256K x 36/512K x 18) Pipelined SRAM Document Number: 38-05540 REV. ECN NO. Issue Date ** 241690 See ECN *A 278130 See ECN *B 248929 See ECN *C 323636 See ECN Document #: 38-05540 Rev. *C PRELIMINARY Orig. of Change RKF New data sheet RKF Changed Boundary Scan order to match the B rev of these devices ...