M29DW128F60NF1 STMICROELECTRONICS [STMicroelectronics], M29DW128F60NF1 Datasheet - Page 45

• Manufacturer Part Number: M29DW128F60NF1
• Description: 128 Mbit (16Mb x8 or 8Mb x16, Multiple Bank, Page, Boot Block) 3V Supply, Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M29DW128F
7
7.1
7.2
Status Register
The M29DW128F has one Status Register. The Status Register provides information on the
current or previous Program or Erase operations executed in each bank. The various bits
convey information and errors on the operation. Bus Read operations from any address within
the Bank, always read the Status Register during Program and Erase operations. It is also read
during Erase Suspend when an address within a block being erased is accessed.
The bits in the Status Register are summarized in
Data Polling Bit (DQ7)
The Data Polling Bit can be used to identify whether the Program/Erase Controller has
successfully completed its operation or if it has responded to an Erase Suspend. The Data
Polling Bit is output on DQ7 when the Status Register is read.
During Program operations the Data Polling Bit outputs the complement of the bit being
programmed to DQ7. After successful completion of the Program operation the memory returns
to Read mode and Bus Read operations from the address just programmed output DQ7, not its
complement.
During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state of
DQ7. After successful completion of the Erase operation the memory returns to Read mode.
In Erase Suspend mode the Data Polling Bit will output a ’1’ during a Bus Read operation within
a block being erased. The Data Polling Bit will change from a ’0’ to a ’1’ when the Program/
Erase Controller has suspended the Erase operation.
Figure 8: Data Polling
Address is the address being programmed or an address within the block being erased.
Toggle Bit (DQ6)
The Toggle Bit can be used to identify whether the Program/Erase Controller has successfully
completed its operation or if it has responded to an Erase Suspend. The Toggle Bit is output on
DQ6 when the Status Register is read.
During a Program/Erase operation the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations at any address. After successful completion of the operation
the memory returns to Read mode.
During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block
being erased. The Toggle Bit will stop toggling when the Program/Erase Controller has
suspended the Erase operation.
Figure 9: Toggle
Figure 17
describe Toggle Bit timing waveform.
Flowchart, gives an example of how to use the Data Toggle Bit.
Flowchart, gives an example of how to use the Data Polling Bit. A Valid
Table 19: Status Register
Bits.
7 Status Register
Figure 16
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