ICS8302AM ICST [Integrated Circuit Systems], ICS8302AM Datasheet
ICS8302AM
Manufacturer Part Number
ICS8302AM
Description
LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER
Manufacturer
ICST [Integrated Circuit Systems]
Datasheet
1.ICS8302AM.pdf
(9 pages)
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B
G
input accepts LVCMOS or LVTTL input levels. The ICS8302
features a pair of LVCMOS/LVTTL outputs. The ICS8302 is
characterized at full 3.3V for input V
2.5V for output operating supply modes (V
teed output and par t-to-par t skew characteristics make
the ICS8302 ideal for clock distribution applications demand-
ing well defined performance and repeatibility.
8302AM
HiPerClockS™
ICS
LOCK
ENERAL
CLK
D
The ICS8302 is a low skew, 1-to-2 LVCMOS
Fa n o u t B u f f e r a n d a m e m b e r o f t h e
HiPerClock S™ family of High Performance
Clock Solutions from ICS. The ICS8302 has a
single ended clock input. The single ended clock
IAGRAM
Integrated
Circuit
Systems, Inc.
D
ESCRIPTION
DD
Q0
Q1
, and mixed 3.3V and
www.icst.com/products/hiperclocks.html
DDO
). Guaran-
1
F
• 2 LVCMOS / LVTTL outputs
• LVCMOS / LVTTL clock input accepts LVCMOS
• Maximum output frequency: 200MHz
• Output skew: 25ps (typical)
• Part-to-part skew: 250ps (typical)
• Small 8 lead SOIC package saves board space
• Full 3.3V or 3.3V core, 2.5V supply modes
• 0°C to 70°C ambient operating temperature
• Lead-Free package available
• Industrial temperature information available upon request
P
or LVTTL input levels
EATURES
IN
A
LVCMOS / LVTTL F
SSIGNMENT
3.8mm x 4.8mm, x 1.47mm package body
GND
V
CLK
V
DDO
DD
8-Lead SOIC
ICS8302
M Package
Top View
1
2
3
4
8
7
6
5
L
OW
Q0
GND
V
Q1
DDO
ANOUT
S
ICS8302
KEW
REV. C JUNE 15, 2004
, 1-
B
UFFER
TO
-2
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ICS8302AM Summary of contents
Page 1
Integrated Circuit Systems, Inc ENERAL ESCRIPTION The ICS8302 is a low skew, 1-to-2 LVCMOS ICS ...
Page 2
Integrated Circuit Systems, Inc ABLE IN ESCRIPTIONS ...
Page 3
Integrated Circuit Systems, Inc BSOLUTE AXIMUM ATINGS Supply Voltage Inputs, V -0. Outputs, V -0. Package Thermal Impedance, JA Storage Temperature, T -65°C to 150°C STG T 3A. P ...
Page 4
Integrated Circuit Systems, Inc ABLE OWER UPPLY HARACTERISTICS ...
Page 5
Integrated Circuit Systems, Inc. P ARAMETER 1.65V± DDO LVCMOS GND -1.65V±5% 3. UTPUT OAD EST IRCUIT PART PART sk(pp) P ...
Page 6
Integrated Circuit Systems, Inc ABLE VS IR LOW ABLE FOR JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The ...
Page 7
Integrated Circuit Systems, Inc ACKAGE UTLINE UFFIX FOR EAD T ABLE Reference Document: JEDEC Publication 95, MS-012 8302AM LVCMOS / LVTTL F SOIC ACKAGE IMENSIONS ...
Page 8
Integrated Circuit Systems, Inc ABLE RDERING NFORMATION ...
Page 9
Integrated Circuit Systems, Inc & T ...