ICS830-21I ICST [Integrated Circuit Systems], ICS830-21I Datasheet

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ICS830-21I

Manufacturer Part Number
ICS830-21I
Description
2.5V, 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR
Manufacturer
ICST [Integrated Circuit Systems]
Datasheet
B
83021AMI
G
following input types: LVPECL, LVDS, LVHSTL, SSTL, and
HCSL. The small 8-lead SOIC footprint makes this device
ideal for use in applications with limited board space.
HiPerClockS™
IC S
LOCK
ENERAL
D
T h e I C S 8 3 021I i s a 1 - t o -1 Differential-to-
LVCMOS/LVTTL Translator and a member of
the HiPerClockS™ family of High Perfor-
mance Clock Solutions from ICS. The differ-
ential input is highly flexible and can accept the
IAGRAM
nCLK
Integrated
Circuit
Systems, Inc.
D
CLK
ESCRIPTION
Q0
2.5V, 3.3V D
www.icst.com/products/hiperclocks.html
IFFERENTIAL
1
F
P
One LVCMOS / LVTTL output
Differential CLK, nCLK input pair
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Maximum output frequency: 350MHz (typical)
Part-to-part skew: 500ps (maximum)
Additive phase jitter, RMS: 0.21ps (typical), 3.3V output
Small 8 lead SOIC package saves board space
Full 3.3V, 2.5V operating supply
-40°C to 85°C ambient operating temperature
Available in both standard and lead-free RoHS-compliant
packages
EATURES
IN
A
-
SSIGNMENT
3.8mm x 4.8mm, x 1.47mm package body
TO
-LVCMOS/LVTTL T
nCLK
CLK
nc
nc
ICS83021I
8-Lead SOIC
M Package
Top View
1
2
3
4
8
7
6
5
V
Q0
nc
GND
DD
ICS83021I
REV. C DECEMBER 12, 2005
RANSLATOR
1-
TO
-1

Related parts for ICS830-21I

ICS830-21I Summary of contents

Page 1

... Available in both standard and lead-free RoHS-compliant packages SSIGNMENT 3.8mm x 4.8mm, x 1.47mm package body www.icst.com/products/hiperclocks.html 1 ICS83021I 1- -LVCMOS/LVTTL T RANSLATOR CLK nCLK GND ICS83021I 8-Lead SOIC M Package Top View REV. C DECEMBER 12, 2005 -1 TO ...

Page 2

... www.icst.com/products/hiperclocks.html 2 ICS83021I -LVCMOS/LVTTL T TO RANSLATOR ...

Page 3

... www.icst.com/products/hiperclocks.html 3 ICS83021I -LVCMOS/LVTTL T RANSLATOR = -40°C 85° ...

Page 4

... www.icst.com/products/hiperclocks.html 4 ICS83021I - -LVCMOS/LVTTL T TO RANSLATOR ...

Page 5

... FFSET ROM ARRIER REQUENCY above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. www.icst.com/products/hiperclocks.html 5 ICS83021I 1- -LVCMOS/LVTTL T RANSLATOR @ 100MHz (12kHz to 20MHz) = 0.21ps typical 10M 100M ( REV. C DECEMBER 12, 2005 ...

Page 6

... O L UTPUT PART 1 Qx PART 2 V CMR ART TO ART UTPUT UTY 2V 0.8V 20% Clock t Outputs F 2.5V O UTPUT www.icst.com/products/hiperclocks.html 6 ICS83021I 1- -LVCMOS/LVTTL T RANSLATOR SCOPE OAD EST IRCUIT tsk(pp) S KEW PERIOD 100% odc = t ...

Page 7

... For example, if the input DD clock swing is only 2.5V and V and R2/R1 = 0.609. VDD R1 1K CLK V_REF nCLK C1 0. INGLE NDED IGNAL RIVING IFFERENTIAL www.icst.com/products/hiperclocks.html 7 ICS83021I 1- -LVCMOS/LVTTL T RANSLATOR = 3.3V, V_REF should be 1.25V DD I NPUT REV. C DECEMBER 12, 2005 -1 TO ...

Page 8

... HiPerClockS Input 2D. H NPUT RIVEN BY IGURE 3.3V R4 125 CLK nCLK HiPerClockS Input NPUT RIVEN OUPLE www.icst.com/products/hiperclocks.html 8 ICS83021I 1- -LVCMOS/LVTTL T RANSLATOR 3. Ohm CLK Ohm nCLK HiPerClockS Input CLK/nCLK LOCK NPUT RIVEN BY 3.3V LVPECL D RIVER 3 ...

Page 9

... Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs RANSISTOR OUNT The transistor count for ICS83021I is: 416 Pin-to-pin compatible with MC100EPT21 83021AMI 2.5V, 3. IFFERENTIAL TO ...

Page 10

... ° 0 www.icst.com/products/hiperclocks.html 10 ICS83021I 1- -LVCMOS/LVTTL T RANSLATOR ° 8 REV. C DECEMBER 12, 2005 ...

Page 11

... " " " www.icst.com/products/hiperclocks.html 11 ICS83021I -LVCMOS/LVTTL T TO RANSLATOR ° ...

Page 12

... www.icst.com/products/hiperclocks.html 12 ICS83021I -LVCMOS/LVTTL T TO RANSLATOR ...

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