ICS830-21I ICST [Integrated Circuit Systems], ICS830-21I Datasheet - Page 7

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ICS830-21I

Manufacturer Part Number
ICS830-21I
Description
2.5V, 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR
Manufacturer
ICST [Integrated Circuit Systems]
Datasheet
W
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
83021AMI
IRING THE
D
Integrated
Circuit
Systems, Inc.
IFFERENTIAL
I
NPUT TO
F
IGURE
Single Ended Clock Input
2.5V, 3.3V D
1. S
A
A
www.icst.com/products/hiperclocks.html
CCEPT
INGLE
PPLICATION
E
C1
0.1u
NDED
S
V_REF
INGLE
DD
S
/2 is
IGNAL
IFFERENTIAL
E
NDED
7
I
D
NFORMATION
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
and R2/R1 = 0.609.
RIVING
1K
R1
1K
R2
VDD
L
EVELS
D
IFFERENTIAL
CLK
nCLK
-
TO
-LVCMOS/LVTTL T
I
NPUT
DD
= 3.3V, V_REF should be 1.25V
ICS83021I
REV. C DECEMBER 12, 2005
RANSLATOR
1-
TO
-1

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