CY7C138 CYPRESS [Cypress Semiconductor], CY7C138 Datasheet - Page 2

• Manufacturer Part Number: CY7C138
• Description: 4K x 8/9 Dual-Port Static RAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Pin Configurations
\
Notes:
Pin Definitions
Selection Guide
I/O
A
CE
OE
R/W
SEM
INT
BUSY
M/S
V
GND
Maximum Access Time (ns)
Maximum Operating
Current (mA)
Maximum Standby
Current for I
3.
4.
0L–11L
CC
0L–7L(8L)
L
L
I/O
I/O
L
L
L
8R
8L
L
on the CY7C139.
Left Port
on the CY7C139.
SB1
(mA)
I/O
A
CE
OE
R/W
SEM
INT
BUSY
0R–11R
0R–7R(8R)
R
R
R
R
R
R
Commercial
Commercial
Right Port
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
V
V
CC
CC
0R
1R
2R
3R
4R
5R
6R
2L
3L
4L
5L
6L
7L
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
2728 29 30
9 8 7 6
Data Bus Input/Output
Address Lines
Chip Enable
Output Enable
Read/Write Enable
Semaphore Enable. When asserted LOW, allows access to eight sema-
phores. The three least significant bits of the address lines will determine
which semaphore to write or read. The I/O
semaphore. Semaphores are requested by writing a 0 into the respective
location.
Interrupt Flag. INT
when left port reads location FFE. INT
FFF and is cleared when right port reads location FFF.
Busy Flag
Master or Slave Select
Power
Ground
3132 33 34 35 36 37 38 39 40 41 42 43
5 4 3 2 1 68
68-Pin PLCC
7C138-15
7C139-15
CY7C138/9
Top View
220
15
60
2
67
66 65 64 63 62 61
L
is set when right port writes location FFE and is cleared
7C138-25
7C139-25
180
25
40
C138-2
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
Description
A
A
A
A
A
A
INT
BUSY
GND
M/S
BUSY
INT
A
A
A
A
A
5L
4L
3L
2L
1L
0L
0R
1R
2R
3R
4R
L
R
L
R
R
is set when left port writes location
7C138-35
7C139-35
0
pin is used when writing to a
160
35
30
CY7C138
CY7C139
7C138-55
7C139-55
160
55
30