CY7C135 CYPRESS [Cypress Semiconductor], CY7C135 Datasheet - Page 7

• Manufacturer Part Number: CY7C135
• Description: 4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Waveforms
Notes:
Document #: 38-06038 Rev. *B
18. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can
19. R/W must be HIGH during all address transactions.
20. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
21. Data I/O pins enter high-impedance when OE is held LOW during write.
Write Cycle No. 2:R/W Three-States Data I/Os (Either Port)
Write Cycle No. 1: OE Three-States Data I/Os (Either Port)
ADDRESS
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
bus for the required t
t
ADDRESS
PWE
DATA
DATA
SEM
DATA
SEM
DATA
OR CE
.
OR CE
R/W
OUT
R/W
OE
OUT
[13]
IN
IN
[13]
SD
. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write pulse can be as short as the specified
t
SA
(continued)
t
SA
t
HZOE
t
SCE
t
t
AW
SCE
t
HIGH IMPEDANCE
t
AW
HZWE
t
WC
t
[18,19,20]
[19, 21]
WC
t
PWE
t
PWE
PWE
or (t
HZWE
t
SD
DATA VALID
+ t
t
HIGH IMPEDANCE
SD
DATA VALID
SD
) to allow the I/O drivers to turn off and data to be placed on the
t
t
t
HD
LZWE
HA
t
LZOE
t
HA
t
HD
CY7C1342
CY7C135
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