ICS601-01 ICST [Integrated Circuit Systems], ICS601-01 Datasheet

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ICS601-01

Manufacturer Part Number
ICS601-01
Description
Low Phase Noise Clock Multiplier
Manufacturer
ICST [Integrated Circuit Systems]
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ICS601-01
Manufacturer:
HIMAX
Quantity:
6 400
X1/ICLK
MDS 601-01 G
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com
Description
The ICS601-01 is a low cost, low phase noise, high
performance clock synthesizer for any applications
that require low phase noise and low jitter. It is
ICS’ lowest phase noise multiplier, and also the
lowest CMOS part in the industry. Using ICS’
patented analog and digital Phase Locked Loop
(PLL) techniques, the chip accepts a 10-27 MHz
crystal or clock input, and produces output clocks
up to 156 MHz at 3.3 V.
Block Diagram
X2
Reference
Oscillator
Divide
Crystal
VDD
GND
S3 S2
Comparator
ROM Based
Multipliers
Phase
S1
S0
Charge
Pump
Divide
1
VCO
Low Phase Noise Clock Multiplier
Features
• Packaged in 16 pin SOIC or TSSOP
• Uses fundamental 10 - 27 MHz crystal, or clock
• Patented PLL with the lowest phase noise
• Output clocks up to 156 MHz at 3.3 V
• Low phase noise: -132 dBc/Hz at 10 kHz
• Output Enable function tri states outputs
• Low jitter - 18 ps one sigma
• Full swing CMOS outputs with 25 mA drive
• Advanced, low power, sub-micron CMOS process
• Industrial temperature version available
• 3.3 V or 5 V operation
capability at TTL levels
Filter
Loop
VCO
Revision 090800
OE
Output
Output
Buffer
Buffer
REFEN
ICS601-01
Printed 11/14/00
CLK
REFOUT

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ICS601-01 Summary of contents

Page 1

... Description The ICS601- low cost, low phase noise, high performance clock synthesizer for any applications that require low phase noise and low jitter ICS’ lowest phase noise multiplier, and also the lowest CMOS part in the industry. Using ICS’ ...

Page 2

... Input Input Input Input TEST Crystal osc. pass through (no PLL Input TEST Input Input x10 Input x12 Input x16 Revision 090800 ICS601-01 Printed 11/14/00 ...

Page 3

... Figure 1 shows a typical phase noise measurement in a 125 MHz system. There are a few simple steps that can be taken to achieve these levels of phase noise from the ICS601-01. Variations in VDD will increase the phase noise important to have a stable, low noise supply voltage at the device. Use decoupling capacitors of 0.1 µ ...

Page 4

... Each output ±40 OE, select pins 0.8 to 2.0V, no load 0.8 to 2.0V, no load At VDD load, REF off 100 Hz offset -105 1 kHz offset -120 10 kHz offset -128 100 kHz offset -121 4 ICS601-01 Typical Maximum Units 7 V VDD+0 °C 85 °C 260 °C 150 °C 5 ...

Page 5

... Low Phase Noise Clock Multiplier Marking Shipping packaging ICS601M-01 tubes ICS601M-01 tape and reel ICS601M-01I tubes ICS601M-01I tape and reel ICS601G-01 tubes ICS601G-01 tape and reel 5 ICS601-01 16 pin narrow SOIC, TSSOP (in mm) SOIC SOIC TSSOP TSSOP Symbol Min Max Min A 1.35 1. 0.10 0.25 0.05 B 0.33 ...

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