ICS307-02 ICST [Integrated Circuit Systems], ICS307-02 Datasheet - Page 4

• Manufacturer Part Number: ICS307-02
• Description: SERIALLY PROGRAMMABLE CLOCK SOURCE
• Manufacturer: ICST [Integrated Circuit Systems]

MDS 307-01/02 F
In te grated Circuit Systems
Setting the Device Characteristics
The tables below show the settings which can be configured, as well as the VCO and Reference dividers.
Table 1. Output Divide and Maximum Output Frequency
Table 2. CLK2 Output
Table 3. Output Duty Cycle Configuration
Table 4. Crystal Load Capacitance
Note: The TTL bit optimizes the duty cycle at different VDD. When VDD is 5 V, set to 0 for a near-50% duty
cycle with TTL levels. When VDD is 3.3 V, set this bit to 1 so the 50% duty cycle is achieved at VDD/2.
Note: f is the crystal frequency in MHz between 10 and 27 MHz. Effective load capacitance will be higher
for crystal frequencies lower than 10 MHz. If a clock input is used, set C1 = 0 and C0 = 0.
S2
F1
TTL
0
0
0
0
1
1
1
1
0
0
1
1
C1
0
1
0
0
1
1
S1
F0
0
0
1
1
0
0
1
1
0
1
0
1
C0
0
1
0
1
S0
0
1
0
1
0
1
0
1
Duty Cycle Measured At
OFF (Low)
F
F
CLK2
CLK1
REF
REF
CLK1 Output
/2
/2
●
VDD/2
Divide
1.4 V
525 Ra ce Street, San Jose, CA 9512 6
10
2
8
4
5
7
3
6
22.3 - 0.083 f
23.1 - 0.093 f
23.7 - 0.106 f
24.4 - 0.120 f
VDD = 5V
5 V or 3.3 V (MHz)
Max. Frequency
200
100
135
40
50
80
55
67
4
Recommended VDD
22.1 - 0.094 f
22.9 - 0.108 f
23.5 - 0.120 f
24.2 - 0.135 f
VDD = 3.3V
3.3 V
S
5 V
Industrial Temp. Version
ERIALLY
Max. Frequency
●
tel [phone]
180
120
P
36
45
90
72
50
60
ROGRAMMABLE
●
C
ICS307-01/02
w w w. i c s t . c o m
LOCK
Revision 121304
S
OURCE