ICS2572M ICST [Integrated Circuit Systems], ICS2572M Datasheet - Page 3

• Manufacturer Part Number: ICS2572M
• Description: User-Programmable Dual High-Performance Clock Generator
• Manufacturer: ICST [Integrated Circuit Systems]

Digital Inputs
The FS0-FS3 pins and the STROBE pin are used to select the
desired operating frequency of the VCLK output from the 16
pre-programmed/user-programmed selections in the ICS2572.
These pins are also used to load new frequency data into the
registers.
Available configurations for the STROBE input include: posi-
tive-edge triggered, negative-edge triggered, high-level trans-
parent, and low-level transparent (see Ordering Information).
VCLK Output Frequency Selection
To change the VCLK output frequency, simply write the ap-
propriate data to the ICS2572 FS inputs. Do not perform any
further writes to the device for 50 milliseconds (assumes a
14.318 MHz reference). The synthesizer will output the new
frequency programmed into that location after a brief delay
(see timeout specifications).
MCLK Output Frequency Selection
The MS0-MS1 pins are used to directly select the desired
operating frequency of the MCLK output from the four pre-
programmed/user-programmed selections in the ICS2572.
These inputs are not latched, nor are they involved with mem-
ory programming operations.
Programming Mode Selection
A programming sequence is defined as a period of at least 50
milliseconds of no data writes to the ICS2572 (to clear the shift
register) followed by a series of data writes (as shown here):
E-97
FS0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
FS1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
START bit (must be “0”)
R/W* control
L0 (location LSB)
L1
L2
L3
L4 (location MSB)
N0 (feedback LSB)
N1
N2
N3
N4
N5
N6
N7 (feedback MSB)
EXTFREQ bit (selected if “1”)
D0 (post-divider LSB)
D1 (post-divider MSB)
STOP1 bit (must be “1”
STOP2 bit (must be “1”)
FS2
”
”
”
”
”
”
”
”
”
”
”
”
”
”
”
”
”
”
”
”
ICS2572
FS3
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0