CY7C1214F-100AC CYPRESS [Cypress Semiconductor], CY7C1214F-100AC Datasheet
CY7C1214F-100AC
Related parts for CY7C1214F-100AC
CY7C1214F-100AC Summary of contents
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... Offered in JEDEC-standard 100-pin TQFP package • “ZZ” Sleep Mode option Functional Description [1] The CY7C1214F is a 32,768 x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is Logic Block Diagram A0, A1, A ...
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... SSQ V 27 DDQ Document #: 38-05434 Rev. *A 117 MHz 100 MHz 7.5 8.0 220 205 35 35 100-Pin TQFP CY7C1214F CY7C1214F Unit DDQ 76 V SSQ BYTE ...
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... The direction of the pins is controlled When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs are placed in a three-state condition. Power supply inputs to the core of the device. Ground for the core of the device. CY7C1214F , CE , and CE are 1 ...
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... Maximum access delay from the clock rise ( 7.5 ns (117-MHz device). CDV The CY7C1214F supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486™ processors. The linear burst sequence is suited for processors that utilize a linear burst sequence ...
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... and BWE = L or GW= L. WRITE = H when all Byte Write enable signals CY7C1214F Second Third Address Address Min. Max CYC ...
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... BWE CY7C1214F ADV WRITE OE CLK L L-H Three-State L L-H Three-State L L-H Three-State L L L-H Q ...
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... IL (min.) within 200 ms. During this time V < CY7C1214F Ambient ] Temperature V DD ° ° +70 C 3.3V −5%/+10% CY7C1214F Min. Max. 3.135 3.135 2.4 2 –0.3 −5 –30 –5 –5 –300 8.0-ns cycle, 117 MHz 10-ns cycle, 100 MHz 8.0-ns cycle, 117 MHz 10-ns cycle, 100 MHz All speeds 8 ...
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... V POWER is less than t and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ CY7C1214F TQFP Package 41.83 9.99 Max ALL INPUT PULSES V DDQ 90% ...
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... GW , BWE , BW t Hold after CLK Rise WEH [A:D] t ADV Hold after CLK Rise ADVH t Data Input Hold after CLK Rise DH t Chip Enable Hold after CLK Rise CEH Document #: 38-05434 Rev. *A [10, 11] Description CY7C1214F 117 MHz 100 MHz Min. Max. Min. Max. Unit 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2 ...
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... ADVS ADVH t CDV t OELZ t OEHZ t DOH Q(A2 DON’T CARE is HIGH and CE is LOW. When CE is HIGH CY7C1214F ADV suspends burst. Q( Q(A2) Q( Burst wraps around to its initial state BURST READ UNDEFINED is HIGH LOW HIGH Deselect Cycle ...
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... Full width write can be initiated by either GW LOW HIGH, BWE LOW and BW Document #: 38-05434 Rev WES WEH DH D(A2 BURST WRITE DON’T CARE UNDEFINED [A:D] CY7C1214F ADSC extends burst. t ADS t ADH A3 t WES t WEH t ADVS t ADVH ADV suspends burst D(A3) D( Extended BURST WRITE LOW ...
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... The data bus (Q) remains in High-Z following a Write cycle unless an ADSP , ADSC , or ADV cycle is performed. 19 HIGH Document #: 38-05434 Rev WEH WES OELZ D(A3) t OEHZ t CDV Q(A4) Single WRITE DON’T CARE CY7C1214F A5 D(A5) Q(A4+1) Q(A4+2) Q(A4+3) Back-to-Back BURST READ UNDEFINED Page D(A6) WRITEs ...
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... Speed (MHz) Ordering Code 100 CY7C1214F-100AC Shaded area contain advance information. Please contact your local Cypress sales representative for availability of this part. Please contact your local Cypress sales representative for availability of 117-MHz speed grade option. Notes: 20. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. ...
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... Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. DIMENSIONS ARE IN MILLIMETERS 0.30±0.08 0.65 TYP STAND-OFF 0.05 MIN. SEATING PLANE 0.15 MAX. A CY7C1214F 1.40±0.05 12°±1° A SEE DETAIL (8X) 0.20 MAX. 1.60 MAX. 51-85050-*A Page ...
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... Document History Page Document Title: CY7C1214F 1-Mb (32K x 32) Flow-Through Sync SRAM Document Number: 38-05434 REV. ECN NO. Issue Date ** 200780 See ECN *A 213321 See ECN Document #: 38-05434 Rev. *A Orig. of Change NJY New Data Sheet VBL Updated Ordering info: shaded part number, added explanation ...