AD7885 AD [Analog Devices], AD7885 Datasheet - Page 9

• Manufacturer Part Number: AD7885
• Description: LC2MOS 16-Bit, High Speed Sampling ADCs
• Manufacturer: AD [Analog Devices]

REV. C
Timing and Control Section
Figure 9 shows the timing and control sequence for the
AD7884/AD7885. When the part receives a CONVST pulse,
the conversion begins. The input sample-and-hold goes into the
hold mode 50 ns after the rising edge of CONVST and BUSY
goes low. This is the first phase of conversion and takes 3.35 s
to complete. The second phase of conversion begins when SW2
is turned off and SW3 turned on. The Residue Amplifier and
SHA section (A2 in Figure 8) goes into hold mode at this point
and allows the input sample-and-hold to go back into sample
mode. Thus, while the second phase of conversion is ongoing,
the input sample-and-hold is also acquiring the input signal for
the next conversion. This overlap between conversion and ac-
quisition allows throughput rates of 166 kSPS to be achieved.
USING THE AD7884/AD7885 ANALOG INPUT RANGES
The AD7884/AD7885 can be set up to have either a 3 volts
analog input range or a 5 volts analog input range. Figures 10
and 11 show the necessary corrections for each of these. The
output code is 2s complement and the ideal code table for both
input ranges is shown in Table I.
Reference Considerations
The AD7884/AD7885 operates from a 3 volt reference. This
can be derived simply using the AD780 as shown in Figure 6.
INPUT
SHA
CONVST
BUSY
FIRST PHASE OF CONVERSION
SAMPLE
HOLD
1ST 9-BIT CONVERSION
DAC SETTLING TIME
RESIDUE AMPLIFIER
SETTLING TIME
Figure 9. Timing and Control Sequence
In Terms of FSR
+FSR/2 – 1 LSB
+FSR/2 – 2 LSBs
+FSR/2 – 3 LSBs
AGND + 1 LSB
AGND
AGND – 1 LSB
–(FSR/2 – 3 LSBs)
–(FSR/2 – 2 LSBs)
–(FSR/2 – 1 LSB)
NOTES
1
2
3
4
This table applies for V
FSR (Full-Scale Range) is 6 volts for the 3 V input range and 10 volts for the 5 V input range.
1 LSB on the 3 V range is FSR/2
1 LSB on the 5 V range is FSR/2
FIRST PHASE
3.5 s
2
Table I. Ideal Output Code Table for the AD7884/AD7885
SECOND PHASE OF CONVERSION
REF+
2ND 9-BIT CONVERSION
ERROR CORRECTION
OUTPUT LATCH UPDATE
S = +3 V.
2.999908
2.999817
2.999726
0.000092
0.000000
–0.000092
–2.999726
–2.999817
–2.999908
SECOND
3 V Range
PHASE
1.8 s
16
16
Analog Input
and is equal to 91.5 V.
and is equal to 152.6 V.
TACQ
2.5 s
3
4.999847
4.999695
4.999543
0.000153
0.000000
–0.000153
–4.999543
–4.999695
–4.999847
–9–
5 V Range
The critical performance specification for a reference in a 16-bit
application is noise. The reference pk-pk noise should be insig-
nificant in comparison to the ADC noise. The AD7884/
AD7885 has a typical rms noise of 120 V. For example a rea-
sonable target would be to keep the total rms noise less than
125 V. To do this the reference noise needs to be less than
35 V rms. In the 100 kHz band, the AD780 noise is less than
30 V rms, making it a very suitable reference.
The buffer amplifier used to drive the device V
low enough noise performance so as not to affect the overall
system noise requirement. The AD845 and AD817 achieve
this.
4
V
Figure 11. 3 V Input Range Connections
Figure 10. 5 V Input Range Connection
INV
V
INV
Digital Output
Code Transition
011 . . . 111 to 111 . . . 110
011 . . . 110 to 011 . . . 101
011 . . . 101 to 011 . . . 100
000 . . . 001 to 000 . . . 000
000 . . . 000 to 111 . . . 111
111 . . . 111 to 111 . . . 110
100 . . . 011 to 100 . . . 010
100 . . . 010 to 100 . . . 001
100 . . . 001 to 100 . . . 000
A1
A1
AD7884/AD7885
5V
5V
3V
3V
l
3V
5V
5V
3V
IN
IN
IN
IN
IN
F
IN
IN
IN
S
F
S
S
F
S
F
REF+
should have