CY7C0851V CYPRESS [Cypress Semiconductor], CY7C0851V Datasheet - Page 20

• Manufacturer Part Number: CY7C0851V
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Waveforms
Notes
Document Number: 38-06070 Rev. *L
33. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress CY7C0851V/CY7C0851AV/CY7C0852V/CY7C0852AV
34. ADS = CNTEN= B0 – B3 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.
35. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
36. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
37. CE
38. CE
device from this data sheet. ADDRESS
(labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.
ADDRESS
ADDRESS
0
DATA
DATA
0
= B0 – B3 = R/W = LOW; CE
= OE = B0 – B3 = LOW; CE
ADDRESS
OUT(B2)
DATA
OUT(B1)
CE
CE
DATA
CLK
(B1)
(B1)
(B2)
(B2)
CLK
R/W
OUT
CE
IN
t
t
t
t
SA
SC
SA
SC
t
t
t
SW
SC
SA
A
A
A
0
0
1
1
n
t
= CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be completed
= R/W = CNTRST = MRST = HIGH.
CH2
t
CH2
(continued)
Figure 11. Read-to-Write-to-Read (OE = LOW)
(B1)
t
t
t
t
t
t
CYC2
HC
HC
CYC2
t
HA
HA
t
t
HW
HC
HA
= ADDRESS
t
t
CL2
CL2
A
A
READ
A
n+1
1
1
t
Figure 10. Bank Select Read
CD2
(B2)
t
CD2
.
t
SW
t
SC
Q
n
Q
t
0
SC
A
n+2
A
t
A
CKHZ
NO OPERATION
2
2
t
t
DC
HC
t
HW
t
HC
t
CD2
t
SD
A
D
n+2
n+2
Q
t
HD
A
[33, 34]
A
1
3
t
3
DC
t
t
CKLZ
CKHZ
WRITE
t
[32, 35, 36, 37, 38]
CD2
t
CKLZ
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
A
n+3
t
CD2
A
Q
A
4
2
4
t
t
t
CKHZ
CD2
CKLZ
READ
Q
n+1
A
Q
n+4
3
t
CD2
A
A
5
t
5
t
t
CKLZ
CKHZ
CD2
Q
n+3
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