AD7467BRT AD [Analog Devices], AD7467BRT Datasheet - Page 9

• Manufacturer Part Number: AD7467BRT
• Description: 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23
• Manufacturer: AD [Analog Devices]

REV. PrC
CIRCUIT INFORMATION
The AD7466/AD7467/AD7468 are fast, micro-power, 12/
10/8-bit, A/D converters respectively. The parts can be
operated from a +1.8 V to +3.6 V supply. When operated
from any supply voltage within this range, the AD7466/
AD7467/AD7468 is capable of throughput rates of 100
kSPS when provided with a 2 MHz clock.
The AD7466/AD7467/AD7468 provides the user with an
on-chip track/hold, A/D converter, and a serial interface
housed in a tiny 6-pin SOT-23 package, which offers the
user considerable space saving advantages over alternative
solutions. The serial clock input accesses data from the
part but also provides the clock source for the successive-
approximation A/D converter. The analog input range is 0
to V
and neither is there a reference on-chip. The reference for
the AD7466/AD7467/AD7468 is derived from the power
supply and thus gives the widest dynamic input range.
The AD7466/AD7467/AD7468 also features an automatic
power-down mode option to allow power saving between
conversions. The power-down feature is implemented
across the standard serial interface as described in the
“Modes of Operation” section.
CONVERTER OPERATION
The AD7466/AD7467/AD7468 is a successive approxi-
mation analog-to-digital converter based around a charge
redistribution DAC. Figures 8 and 9 show simplified
schematics of the ADC. Figure 8 shows the ADC during
its acquisition phase. SW2 is closed and SW1 is in posi-
tion A, the comparator is held in a balanced condition and
the sampling capacitor acquires the signal on V
When the ADC starts a conversion, see figure 9, SW2 will
open and SW1 will move to position B causing the com-
parator to become unbalanced. The Control Logic and
the Charge Redistribution DAC are used to add and sub-
tract fixed amounts of charge from the sampling capacitor
to bring the comparator back into a balanced condition.
When the comparator is rebalanced the conversion is com-
plete. The Control Logic generates the ADC output code.
Figure 10 shows the ADC transfer function.
V I N
DD
S W 1
. An external reference is not required for the ADC
A G N D
A
B
C A P A C I T O R
S A M P L I N G
Figure 8. ADC Acquisition Phase
A C Q U I S I T I O N
V D D / 2
P H A S E
S W 2
C O M P A R A T O R
IN
R E D I S T R I B U T I O N
pecifications
.
C H A R G E
C O N T R O L
L O G I C
D A C
–9–
V IN
ADC TRANSFER FUNCTION
The output coding of the AD7466/AD7467/AD7468 is
straight binary. The designed code transitions occur at
successive integer LSB values (i.e., 1LSB, 2LSBs, etc.).
The LSB size is = V
is = V
V
for the AD7466/AD7467/AD7468 is shown in figure 10
below.
DD
/256 for the AD7468 . The ideal transfer characteristic
Figure 10. AD7466/67/68 Transfer Characteristic
SW1
DD
A
AGND
111...111
111...110
111...000
011...111
000...010
000...001
000...000
/1024 for the AD7467, and the LSB size is =
B
CAPACITOR
Figure 9. ADC Conversion Phase
SAMPLING
CONVERSION
0V
PHASE
V DD / 2
AD7466/AD7467/AD7468
1LSB
DD
ANALOG INPUT
/4096 for the AD7466,the LSB size
SW2
1LSB = V DD /4096 (AD7466)
1LSB = V DD /1024 (AD7467)
1LSB = V DD /256 (AD7468)
+V DD -1LSB
COMPAR ATOR
REDISTRIBUTION
CHARGE
CONTROL
DAC
LOGIC