AD7467BRT AD [Analog Devices], AD7467BRT Datasheet - Page 5

• Manufacturer Part Number: AD7467BRT
• Description: 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23
• Manufacturer: AD [Analog Devices]

Parameter
f
t
t
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
4
5
Specifications subject to change without notice.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7466/AD7467/AD7468 feature proprietary ESD protection circuitry, per-
manent damage may occur on devices subjected to high energy electrostatic discharges. There-
fore, proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
REV. PrC
ABSOLUTE MAXIMUM RATINGS
(T
V
Analog Input Voltage to GND
Digital Input Voltage to GND
Digital Output Voltage to GND
Input Current to Any Pin Except Supplies
Operating Temperature Range
Junction Temperature
SOT-23 Package, Power Dissipation
E S D
NOTES
1
2
TIMING SPECIFICATIONS
SCLK
CONVERT
quiet
1
2
3
4
5
6
7
8
power-up
Mark/Space ratio for the SCLK input is 40/60 to 60/40.
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.
t
See Power-up Time section.
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
part and is independent of the bus loading.
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
Transient currents of up to 100 mA will not cause SCR latch up.
8
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
3
3
4
DD
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to
A
Commercial (A, B Version)
Storage Temperature Range
Lead Temperature, Soldering
JA
JC
= +25°C unless otherwise noted)
2
Vapor Phase (60 secs)
Infared (15 secs)
to GND
Thermal Impedance
5
Thermal Impedance
10
T B D
16* t
T B D
T B D
10
T B D
T B D
0.4t
0.4t
T B D
T B D
T B D
AD7466
SCLK
SCLK
SCLK
1
Units
kHz min
MHz max
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
(V
–0.3 V to V
–0.3 V to V
s typ
1
DD
229.6°C/W (SOT23)
205.9°C/W (µSOIC)
43.74°C/W (µSOIC)
91.99°C/W (SOT23)
= +1.8 V to +3.6 V; T
–0.3 V to TBD V
–65°C to +150°C
–0.3 V to TBDV
2
–40°C to +85°C
pecifications
DD
DD
450 mW
±10 mA
+150°C
+215°C
+220°C
+ 0.3 V
+ 0.3 V
T B D
Description
and start of next conversion
Minimum
SCLK Low Pulse Width
SCLK to Data Valid Hold Time
SCLK High Pulse Width
Power up time from Full Power-down.
Data Access Time After SCLK Falling Edge
Delay from
SCLK falling Edge to SDATA High Impedance
Minimum Quiet Time required between Bus Relinquish
A
= T
–5–
to SCLK Setup Time
MIN
to T
8
, quoted in the timing characteristics is the true bus relinquish time of the
MAX
Figure 1. Load Circuit for Digital Output Timing
Pulse Width
, unless otherwise noted.)
Until SDATA 3-State Disabled
O UT P UT
P IN
T O
AD7466/AD7467/AD7468
DD
C L
50p F
) and timed from a voltage level of 1.6 Volts.
Specifications
200µ A
200µ A
I O L
I O H
+1.6V