CY7C027 CYPRESS [Cypress Semiconductor], CY7C027 Datasheet
CY7C027
Available stocks
Related parts for CY7C027
CY7C027 Summary of contents
Page 1
... Features • True Dual-Ported memory cells which allow simulta- neous access of the same memory location • 32K x 16 organization (CY7C027) • 64K x 16 organization (CY7C028) • 32K x 18 organization (CY7C037) • 64K x 18 organization (CY7C038) • 0.35-micron CMOS for optimum speed/power [1] • ...
Page 2
... Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by the chip enable pins. The CY7C027/028 and CY7C037/038 are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages. 100-Pin TQFP (Top View) ...
Page 3
... A9R 73 A10R 72 A11R 71 A12R 70 A13R 69 A14R 68 A15R 67 LBR 66 UBR 65 CE0R 64 CE1R 63 SEMR 62 R/WR 61 GND 60 OER 59 GND 58 I/O17R 57 GND 56 I/O16R 55 I/O15R 54 I/O14R 53 I/O13R 52 I/O12R 51 I/O11R CY7C027/028 CY7C027/028 CY7C037/038 CY7C037/038 [1] -12 - 195 190 55 50 0.05 0.05 [7] -20 20 180 45 0.05 Page ...
Page 4
... Interrupt Flag Busy Flag Master or Slave Select Power Ground No Connect Input Voltage Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... >1100V Latch-Up Current.................................................... >200 mA Operating Range Range Commercial Industrial CY7C027/028 CY7C037/038 Description V and –A for 64K devices – ...
Page 5
... Ind. Com’ [10] R Ind. Com’l. 125 205 , [10] IH Ind. Com’l. 0.05 0.5 & [10] Ind. Com’l. 115 185 [10] Ind. CY7C027/028 CY7C037/038 CY7C027/028 CY7C037/038 -15 -20 Min. Typ. Max. Min. Typ. 2.4 2.4 0.4 2.2 2.2 0.8 –10 10 –10 190 280 180 305 120 180 ...
Page 6
... (b) Thévenin Equivalent (Load 1) ALL INPUT PULSES 3.0V 90% 10% GND 3 ns [13] 1.00 0.90 0.80 0.70 = 1.4V 0.60 TH 0.50 0.40 0.30 0.20 0.10 0. CY7C027/028 CY7C037/038 Max OUTPUT 1.4V TH (c) Three-State Delay (Load 2) (Used for CKLZ OLZ including scope and jig) 90% 10 Capacitance (pF) (b) Load Derating Curve ...
Page 7
... HZCE LZCE HZOE LZOE CY7C027/028 CY7C037/038 -20 Min. Max. Unit ...
Page 8
... SEM Address Access Time SAA Data Retention Mode The CY7C027/028 and CY7C037/038 are designed with bat- tery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip enable (CE) must be held HIGH during data retention, with- ...
Page 9
... DOE t LZOE t LZCE LZCE t ABE t ACE t LZCE and This waveform cannot be used for semaphore reads access semaphore SEM = CY7C027/028 CY7C037/038 t OHA DATA VALID t HZCE t HZOE DATA VALID OHA t HZCE t HZCE . IL Page ...
Page 10
... SD [28, 29, 30, 34, 35 SCE LOW CE or SEM and a LOW UB or LB. PWE PWE , SEM = CY7C027/028 CY7C037/038 [34] t HZOE LZWE NOTE allow the I/O drivers to turn off and data to be placed on HZWE SD ...
Page 11
... SPS Document #: 38-06042 Rev. *A [37 SCE t SD DATA VALID PWE t SWRD t SOP WRITE CYCLE [38, 39, 40] MATCH t SPS MATCH = CE = HIGH CY7C027/028 CY7C037/038 t t SAA OHA VALID ADRESS t ACE t SOP DATA VALID OUT t DOE READ CYCLE Page ...
Page 12
... DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 41 LOW Document #: 38-06042 Rev. *A [41 MATCH t PWE t SD VALID MATCH t BLA t PWE CY7C027/028 CY7C037/038 BHA t BDD t DDD VALID t WDD Page ...
Page 13
... BUSY will be asserted. PS Document #: 38-06042 Rev. *A [42] ADDRESS MATCH BLC ADDRESS MATCH BLC [42 ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA CY7C027/028 CY7C037/038 t BHC t BHC Page ...
Page 14
... INS INR Document #: 38-06042 Rev [43 [44] t INR t WC [43 [44] [44] t INR ) is deasserted first R asserted last CY7C027/028 CY7C037/038 t RC READ 7FFF (FFFF for CY7C028/38 READ 7FFE (FFFE for CY7C028/38) Page ...
Page 15
... The upper two memory locations may be used for message passing. The highest memory location (7FFF for the CY7C027/37, FFFF for the CY7C028/38) is the mailbox for the right port and the second-highest memory location (7FFE for the CY7C027/37, FFFE for the CY7C028/38) is the mailbox for the left port. When one port writes to the other port’ ...
Page 16
... Semaphore free 1 0 Right port has semaphore token 1 1 Semaphore free 0 1 Left port has semaphore token 1 1 Semaphore free CY7C027/028 CY7C037/038 I/O –I/O Operation 0 8 High Z Deselected: Power-Down High Z Deselected: Power-Down High Z Write to Upper Byte Only Data In Write to Lower Byte Only ...
Page 17
... Thin Quad Flat Pack Package Name Package Type A100 100-Pin Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack CY7C027/028 CY7C037/038 Operating Range Commercial Commercial Commercial Operating Range Commercial Commercial Commercial ...
Page 18
... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C027/028 CY7C037/038 ...
Page 19
... Document Title: CY7C027/028, CY7C037/038 32K/64K x 16/18 Dual-Port Static RAM Document Number: 38-06042 Issue REV. ECN NO. Date ** 110190 09/29/01 *A 122292 12/27/02 Document #: 38-06042 Rev. *A Orig. of Change Description of Change SZV Change from Spec number: 38-00666 to 38-06042 RBI Power up requirements added to Maximum Ratings Information CY7C027/028 CY7C037/038 Page ...