CY7B991-2 CYPRESS [Cypress Semiconductor], CY7B991-2 Datasheet - Page 6

• Manufacturer Part Number: CY7B991-2
• Description: Programmable Skew Clock Buffer
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Characteristics
Document #: 38-07138 Rev. **
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
13. Test measurement levels for the CY7B991 are TTL levels (1.5V to 1.5V). Test measurement levels for the CY7B992 are CMOS levels (V
14. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
15. Except as noted, all CY7B992–2 and –5 timing parameters are specified to 80-MHz with a 30-pF load.
16. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same t
17. t
18. t
19. C
20. There are three classes of outputs: Nominal (multiple of t
21. t
22. t
23. Specified with outputs loaded with 30 pF for the CY7B99X–2 and –5 devices and 50 pF for the CY7B99X–7 devices. Devices are terminated through 50 to
24. t
25. t
26. t
NOM
RPWH
RPWL
U
SKEWPR
SKEW0
SKEW1
SKEW2
SKEW3
SKEW4
DEV
PD
ODCV
PWH
PWL
ORISE
OFALL
LOCK
JR
Parameter
conditions assume signal transition times of 2 ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified.
loaded with 50 pF and terminated with 50 to 2.06V (CY7B991) or V
or Divide-by-4 mode).
2.06V (CY7B991) or V
is measured from the application of a new signal or frequency at REF or FB until t
SKEWPR
SKEW0
DEV
ODCV
PWH
ORISE
LOCK
L
=0 pF. For C
is the output-to-output skew between any two devices operating under the same conditions (V
is measured at 2.0V for the CY7B991 and 0.8 V
is the time that is required before synchronization is achieved. This specification is valid only after V
is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in t
and t
is defined as the skew between outputs when they are selected for 0t
is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0t
OFALL
Operating Clock
Frequency in MHz
REF Pulse Width HIGH
REF Pulse Width LOW
Programmable Skew Unit
Zero Output Matched-Pair Skew
(XQ0, XQ1)
Zero Output Skew (All Outputs)
Output Skew (Rise-Rise, Fall-Fall, Same
Class Outputs)
Output Skew (Rise-Fall, Nominal-Inverted,
Divided-Divided)
Output Skew (Rise-Rise, Fall-Fall, Different
Class Outputs)
Output Skew (Rise-Fall, Nominal-Divided,
Divided-Inverted)
Device-to-Device Skew
Propagation Delay, REF Rise to FB Rise
Output Duty Cycle Variation
Output HIGH Time Deviation from 50%
Output LOW Time Deviation from 50%
Output Rise Time
Output Fall Time
PLL Lock Time
Cycle-to-Cycle Output
Jitter
L
=30 pF, t
measured between 0.8V and 2.0V for the CY7B991 or 0.8V
CC
SKEW0
/2 (CY7B992).
[16, 17]
=0.35 ns.
[16, 20]
[16, 20]
[26]
Description
[16, 20]
[23, 25]
[16, 20]
[23, 25]
Over the Operating Range
[14, 21]
FS = LOW
FS = MID
FS = HIGH
RMS
Peak-to-Peak
[22]
CC
for the CY7B992. t
[16, 18,19]
[14]
U
delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2
[1, 2]
[1, 2]
[1, 2 , 3]
[23, 24]
[23, 24]
CC
[14]
/2 (CY7B992).
[2, 13]
PWL
U
. Other outputs are divided or inverted but not shifted.
CC
is measured at 0.8V for the CY7B991 and 0.2 V
PD
and 0.2V
–0.25
–0.65
Min.
0.15
0.15
5.0
5.0
15
25
40
is within specified limits.
CY7B991–2
CC
for the CY7B992.
Typ.
0.05
0.25
0.25
0.1
0.3
0.5
0.0
0.0
1.0
1.0
CC
ambient temperature, air flow, etc.)
SKEW2
CC
[14]
+0.25
+0.65
Max.
is stable and within normal operating limits. This parameter
0.20
0.25
0.75
200
0.5
0.5
0.5
0.9
2.0
1.5
1.2
1.2
0.5
30
50
80
25
and t
U
.
SKEW4
See Table 1
–0.25
–0.5
Min.
5.0
5.0
0.5
0.5
15
25
40
specifications.
CY7B992–2
CC
U
delay has been selected when all are
for the CY7B992.
Typ.
0.05
0.25
0.25
0.1
0.3
0.5
0.0
0.0
2.0
2.0
[14]
+0.25
CC
Max.
80
+0.5
CY7B991
CY7B992
0.20
0.25
0.75
200
0.5
0.5
0.5
0.7
3.0
3.0
2.5
2.5
0.5
30
50
25
/2 to V
[15]
Page 6 of 15
CC
/2). Test
MHz
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps