CY7B923-400JI CYPRESS [Cypress Semiconductor], CY7B923-400JI Datasheet - Page 18

• Manufacturer Part Number: CY7B923-400JI
• Manufacturer: CYPRESS [Cypress Semiconductor]

mitter BIST loop to run while the Receiver runs in normal
mode. The BIST loop includes deliberate violation symbols
and will adequately test the RVS function.
BIST mode is intended to check the entire function of the
Transmitter (except the Transmitter input pins and the bypass
function in the Encoder), the serial link, and the Receiver. It
augments normal factory ATE testing and provides the design-
er with a rigorous test mechanism to check the link transmis-
sion system without requiring any significant system overhead.
While in Bypass mode, the BIST logic will function in the same
way as in the Encoded mode. MODE = HIGH and BISTEN =
LOW causes the Transmitter to switch to Encoded mode and begin
sending the BIST pattern, as if MODE = LOW. When BISTEN re-
turns to HIGH, the Transmitter resumes normal Bypass operation. In
Test mode the BIST function works as in the Normal mode. For more
information on BIST, consult the “HOTLink Built-In Self-Test” Applica-
tion Note.
Test Mode
The MODE input pin selects between three transmitter func-
tional modes. When wired to VCC, the D(
Encoder and load directly from the Input register into the Shifter.
When wired to GND, the inputs D
using the Fibre Channel 8B/10B codes and sequences (shown at the
end of this datasheet). Since the Transmitter is usually hard wired to
Encoded or Bypass mode and not switched between them, a third
function is provided for the MODE pin. Test mode is selected by float-
ing the MODE pin (internal resistors hold the MODE pin at VCC/2).
Test mode is used for factory or incoming device test.
Test mode causes the Transmitter to function in its Encoded
mode, but with OutA+/OutB+ (used as a differential test clock
input) as the bit rate clock input instead of the internal
PLL-generated bit clock. In this mode, inputs are clocked by
CKW and transfers between the Input register and Shifter are
timed by the internal counters. The bit-clock and CKW must
maintain a fixed phase and divide-by-ten ratio. The phase and
pulse width of RP are controlled by phases of the bit counter (PLL
feedback counter) as in Normal mode. Input and output patterns can
be synchronized with internal logic by observing the state of RP or the
device can be initialized to match an ATE test pattern using the follow-
ing technique:
Test mode is intended to allow logical, DC, and AC testing of
the Transmitter without requiring that the tester check output
data patterns at the bit rate, or accommodate the PLL lock,
tracking, and frequency range characteristics that are required
when the HOTLink part operates in its normal mode. To use
OutA+/OutB+ as the test clock input, the FOTO input is held
HIGH while in Test mode. This forces the two outputs to go to
an “PECL LOW,” which can be ignored while the test system
creates a differential input signal at some higher voltage.
1. With the MODE pin either HIGH or LOW, stop CKW and
2. Force the MODE pin to MID (open or V
3. Start the bit-clock and let it run for at least 2 cycles.
4. Start the CKW clock at the bit-clock/10 rate.
clocks are stopped.
bit-clock.
0 7
, SVS, and SC/D are encoded
a j
CC
) inputs bypass the
/2) while the
18
CY7B933 HOTLink Receiver Operating Mode
Description
In normal user operation, the Receiver can operate in either of
two modes. The Encoded mode allows a user system to send
and receive 8-bit data and control information without first con-
verting it to transmission characters. The Bypass mode is
used for systems in which the encoding and decoding is per-
formed by an external protocol controller.
In either mode, serial data is received at one of the differential
line receiver inputs and routed to the Shifter and the Clock
Synchronization. The PLL in the Clock Synchronizer aligns
the internally generated bit rate clock with the incoming data
stream and clocks the data into the shifter. At the end of a byte
time (ten bit times), the data accumulated in the shifter is trans-
ferred to the Decode register.
To properly align the incoming bit stream to the intended byte
boundaries, the bit counter in the Clock Synchronizer must be
initialized. The Framer logic block checks the incoming bit
stream for the unique pattern that defines the byte boundaries.
This combinatorial logic filter looks for the X3.230 symbol de-
fined as “Special Character Comma” (K28.5). Once K28.5 is
found, the free running bit counter in the Clock Synchronizer
block is synchronously reset to its initial state, thus “framing”
the data to the correct byte boundaries.
Since noise-induced errors can cause the incoming data to be
corrupted, and since many combinations of error and legal
data can create an alias K28.5, an option is included to disable
resynchronization of the bit counter. The Framer will be inhib-
ited when the RF input is held LOW. When RF rises, RDY will
be inhibited until a K28.5 has been detected, and RDY will
resume its normal function. Data will continue to flow through
the Receiver while RDY is inhibited.
Encoded Mode Operation
In Encoded mode the serial input data is decoded into eight
bits of data (Q
diagnostic output bit (RVS). If the pattern in the Decode register is
found in the Valid Data Characters table, the context of the data is
decoded as normal message data and the SC/D output will be
LOW. If the incoming bit pattern is found in the Valid Special Char-
acter Codes and Sequences table, it is interpreted as “control” or
“protocol information,” and the SC/D output will be HIGH. Special
characters include all protocol characters defined for use in packets
for Fibre Channel, ESCON, and other proprietary and diagnostic
purposes.
The Violation symbol that can be explicitly sent as part of a
user data packet (i.e., Transmitter sending C0.7; D
00000 and SC/D = 1; or SVS = 1) will be decoded and indicated in
exactly the same way as a noise-induced error in the transmission
link. This function will allow system diagnostics to evaluate the error
in an unambiguous manner, and will not require any modification to
the receiver data interface for error-testing purposes.
Bypass Mode Operation
In Bypass mode the serial input data is not decoded, and is
transferred directly from the Decode register to the Output reg-
ister’s 10 bits (Q(
coded prior to transmission, and will be decoded in subsequent log-
ic external to HOTLink. This data can use any encoding method
suitable to the designer. The only restrictions upon the data encod-
ing method is that it contain suitable transition density for the Receiv-
0
a j
Q
). It is assumed that the data has been pre-en-
7
), a context control bit (SC/D), and a system
CY7B923
CY7B933
7 0
= 111