LTC4265 LINER [Linear Technology], LTC4265 Datasheet - Page 8

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LTC4265

Manufacturer Part Number
LTC4265
Description
IEEE 802.3at High Power PD Interface Controller with 2-Event Classifi cation Recognition
Manufacturer
LINER [Linear Technology]
Datasheet

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APPLICATIONS INFORMATION
LTC4265
SIGNATURE CORRUPT OPTION
In some designs that include an auxiliary power option,
it is necessary to prevent a PD from being detected by a
PSE. The LTC4265 signature resistance can be corrupted
with the SHDN pin (Figure 3). Taking the SHDN pin high
will reduce the signature resistor below 11k which is an
invalid signature per the IEEE 802.3af/at specifi cation, and
alerts the PSE not to apply power. Invoking the SHDN pin
also ceases operation for classifi cation and disconnects
the LTC4265 load from the PD input. If this feature is not
used, connect SHDN to V
CLASSIFICATION
Classifi cation provides a method for more effi cient power
allocation by allowing the PSE to identify a PD power clas-
sifi cation. Class 0 is included in the IEEE specifi cation for
PDs that don’t support classifi cation. Class 1-3 partitions
PDs into 3 distinct power ranges. Class 4 includes the new
power range under IEEE802.3at (See Table 2).
8
PSE
TO
Figure 3. 25k Signature Resistor with Disable
SHDN
V
LTC4265
IN
IN
.
14k
TO AUX
25k SIGNATURE
RESISTOR
GND
4265 F03
During classifi cation probing, the PSE presents a fi xed
voltage between 15.5V and 20.5V to the PD (Figure 2).
The LTC4265 asserts a load current representing the PD
power classifi cation. The classifi cation load current is
programmed with a resistor R
Table 2.
Table 2. Summary of Power Classifi cations and LTC4265
R
CLASS
0
1
2
3
4
2-EVENT CLASSIFICATION AND THE T2PSE PIN
A Type-2 PSE may declare the availability of high power by
performing 2-event classifi cation (Layer 1) or by commu-
nicating over the high speed data line (Layer 2). A Type-2
PD must recognize both layers of communication. Since
Layer 2 communications takes place directly between the
PSE and the LTC4265 load, the LTC4265 concerns itself
only with recognizing 2-event classifi cation.
CLASS
Resistor Selection
Optional
Optional
Optional
Optional
USAGE
Default
AT INPUT OF PD
POWER LEVELS
0.44 to 12.95
6.49 to 12.95
12.95 to 25.5
0.44 to 3.84
3.84 to 6.49
MAXIMUM
(W)
CLASS
CLASSIFICATION
LOAD CURRENT
NOMINAL
that is chosen from
(mA)
< 0.4
10.5
18.5
28
40
RESISTOR
LTC4265
(Ω, 1%)
R
Open
69.8
45.3
30.9
CLASS
124
4265f

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