MT312C ZARLINK [Zarlink Semiconductor Inc], MT312C Datasheet - Page 42

• Manufacturer Part Number: MT312C
• Description: Satellite Channel Decoder
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

MT312
B2:
B1:
B0:
6.2 QPSK Demodulator Read Registers
6.2.1 QPSK Interrupt. Registers 0 - 2 (R)
The majority of these interrupts are for diagnostic purposes and generally not useful in normal operation,
unless otherwise indicated.
B7:
B6:
B5:
B4:
B3:
B2:
B1:
B0:
Reading an Interrupt register resets that register.
After the QPSK demodulator achieves Carrier and Timing Lock, from now on referred to as QPSK CT Lock, it
waits some time for the FEC to confirm this lock. When the FEC locks, the QPSK enters QPSK Lock state. The
time QPSK waits for the FEC to gain lock is programmable via register 81 (see section 10.2.31 FEC Lock Time.
Register 81 (R/W)). If the FEC does not achieve lock during this period (very unlikely), then MT312 drops its
QPSK CT Lock status and resumes search for another QPSK signal.
B7:
B6:
B5:
B4:
42
QPSK INT M
QPSK INT H
NAME
NAME
High = QPSK CS LOCK
High = QPSK CT LOCK
Reserved. Must be set low.
High = QPSK Carrier and Timing LOCK important indicator.
High = QPSK Carrier and Timing UNLOCK
High = QPSK LOCKimportant indicator.
High = QPSK UNLOCK
High = QPSK Timing LOCK
High = QPSK Timing UNLOCK
High = QPSK Carrier LOCK
High = QPSK Carrier UNLOCK
High = QPSK FE AGC LOCK
High = QPSK Digital Internal AGC LOCK
High = QPSK Digital Internal AGC UNLOCK
Reserved High = QPSK FR LOCK
QPSK Demodulator
ADR
ADR
00
01
B7
B7
QPSK INT [15:8] Interrupt QPSK (middle byte)
QPSK INT [23:16] Interrupt QPSK (high byte)
B6
B6
B5
B5
B4
B4
B3
B3
B2
B2
B1
B1
B0
B0
R
R
Def
hex
Def
hex
00
00