CS4297-KQ Cirrus Logic, CS4297-KQ Datasheet - Page 39
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CS4297-KQ
Manufacturer Part Number
CS4297-KQ
Description
CrystalClear SoundFusion Audio Codec 97
Manufacturer
Cirrus Logic
Datasheet
1.CS4297-KQ.pdf
(46 pages)
- Current page: 39 of 46
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DS242F5
PIN DESCRIPTIONS
Digital I/O Pins
RESET# - AC’97 Chip Reset, Input
SYNC - AC-link Serial Port Sync pulse, Input
BIT_CLK - AC-link Serial Port Master Clock, Output
CS4297
CrystalClear™ SoundFusion™ Audio Codec ’97
This active low signal is the asynchronous Cold Reset input to the CS4297. The CS4297 must
be reset before it can enter normal operating mode.
This signal is the serial port timing signal for the AC-link of the CS4297. Its period is the
reciprocal of the sample rate of the CS4297, 48 kHz. This signal is generated by the AC’97
Controller and is synchronous to BIT_CLK. SYNC is also an asynchronous input when the
CS4297 is in a Warm Reset state. A series terminating resistor of 47
this signal close to the device driving the signal.
This output signal controls the master clock timing for the AC-link. It is a 12.288 MHz clock
signal which is divided down by two from the XTL_IN input clock. A series terminating
resistor of 47
SDATA_OUT
SDATA_IN
PC_BEEP
XTL_OUT
BIT_CLK
RESET#
should be connected on this signal close to the CS4297.
XTL_IN
DVdd1
DVdd2
DVss1
DVss2
SYNC
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
36
35
34
33
32
31
30
29
28
27
26
25
LINE_OUT_R
LINE_OUT_L
NC
NC
NC
NC
AFLT2
AFLT1
Vrefout
REFFLT
AVss1
AVdd1
should be connected on
39
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