MC68HC711xxxx Motorola, MC68HC711xxxx Datasheet - Page 139

• Manufacturer Part Number: MC68HC711xxxx
• Description: Microcontrollers
• Manufacturer: Motorola

8.7.2 Serial Peripheral Status Register
M68HC11E Family — Rev. 5
MOTOROLA
CPOL — Clock Polarity Bit
CPHA — Clock Phase Bit
SPR[1:0] — SPI Clock Rate Select Bits
SPIF — SPI Interrupt Complete Flag
SPR[1:0]
When the clock polarity bit is cleared and data is not being transferred, the SCK
pin of the master device has a steady state low value. When CPOL is set, SCK
idles high. Refer to
The clock phase bit, in conjunction with the CPOL bit, controls the clock-data
relationship between master and slave. The CPHA bit selects one of two
different clocking protocols. Refer to
Polarity
These two bits select the SPI clock (SCK) rate when the device is configured as
master. When the device is configured as slave, these bits have no effect. Refer
to
SPIF is set upon completion of data transfer between the processor and the
external device. If SPIF goes high, and if SPIE is set, a serial peripheral interrupt
is generated. To clear the SPIF bit, read the SPSR with SPIF set, then access
the SPDR. Unless SPSR is read (with SPIF set) first, attempts to write SPDR
are inhibited.
Address:
0 0
0 1
1 0
1 1
Reset:
Read:
Write:
Table
E Clock By
Controls.
$1029
8-1.
SPIF
Bit 7
Figure 8-4. Serial Peripheral Status Register (SPSR)
0
Divide
16
32
2
4
Serial Peripheral Interface (SPI)
= Unimplemented
WCOL
Figure 8-2
6
0
Frequency at
E = 1 MHz
62.5 kHz
31.3 kHz
Table 8-1. SPI Clock Rates
500 kHz
250 kHz
(Baud)
5
0
and
8.4 Clock Phase and Polarity
MODF
Frequency at
Figure 8-2
4
0
E = 2 MHz
62.5 kHz
1.0 MHz
500 kHz
125 kHz
(Baud)
3
0
and
Serial Peripheral Interface (SPI)
Frequency at
E = 3 MHz (
187.5 kHz
8.4 Clock Phase and
93.8 kHz
1.5 MHz
750 kHz
Baud)
2
0
1
0
Frequency at
SPI Registers
Controls.
E = 4 MHz
250 kHz
125 kHz
(Baud)
2 MHz
1 MHz
Data Sheet
Bit 0
0
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