MC68HC711xxxx Motorola, MC68HC711xxxx Datasheet - Page 135

• Manufacturer Part Number: MC68HC711xxxx
• Description: Microcontrollers
• Manufacturer: Motorola

8.4 Clock Phase and Polarity Controls
8.5 SPI Signals
M68HC11E Family — Rev. 5
MOTOROLA
1. SS ASSERTED
2. MASTER WRITES TO SPDR
3. FIRST SCK EDGE
4. SPIF SET
5. SS NEGATED
(CPHA = 0)
(CPHA = 1)
SAMPLE INPUT
SAMPLE INPUT
SCK (CPOL = 0)
SCK (CPOL = 1)
SS (TO SLAVE)
SCK CYCLE #
DATA OUT
DATA OUT
Software can select one of four combinations of serial clock phase and polarity
using two bits in the SPI control register (SPCR). The clock polarity is specified by
the CPOL control bit, which selects an active high or active low clock, and has no
significant effect on the transfer format. The clock phase (CPHA) control bit selects
one of two different transfer formats. The clock phase and polarity should be
identical for the master SPI device and the communicating slave device. In some
cases, the phase and polarity are changed between transfers to allow a master
device to communicate with peripheral slaves having different requirements.
When CPHA equals 0, the SS line must be negated and reasserted between each
successive serial byte. Also, if the slave writes data to the SPI data register (SPDR)
while SS is low, a write collision error results.
When CPHA equals 1, the SS line can remain low between successive transfers.
This subsection contains descriptions of the four SPI signals:
1
•
•
•
•
2
MSB
3
Master in/slave out (MISO)
Master out/slave in (MOSI)
Serial clock (SCK)
Slave select (SS)
MSB
1
Figure 8-2. SPI Transfer Format
6
Serial Peripheral Interface (SPI)
2
6
SLAVE CPHA = 1 TRANSFER IN PROGRESS
SLAVE CPHA = 0 TRANSFER IN PROGRESS
5
MASTER TRANSFER IN PROGRESS
3
5
4
4
4
3
5
3
2
6
2
Clock Phase and Polarity Controls
1
Serial Peripheral Interface (SPI)
7
1
LSB
8
LSB
4
5
Data Sheet
135