MC68306 Motorola, MC68306 Datasheet - Page 67

• Manufacturer Part Number: MC68306
• Description: Integrated EC000 Processor
• Manufacturer: Motorola

Figure 3-32 shows a synchronous read cycle and the important timing parameters that
apply. The timing for a synchronous read cycle, including relevant timing parameters, is
shown in Figure 3-33.
MOTOROLA
UDS/LDS
CLOCK
DTACK
ADDR
DATA
On the rising edge of the clock, at the end of S7 (which may be the start of
S0 for the next bus cycle), the processor places the address bus in the
high-impedance state. During a write cycle, the processor also places the
data bus in the high-impedance state and drives R/W high. External logic
circuitry should respond to the negation of the AS and UDS /LDS by negating
DTACK and/or BERR . Parameter #28 is the hold time for DTACK, and
parameter #30 is the hold time for BERR .
R/W
AS
6
S0
18
Figure 3-32. Synchronous Read Cycle
S1
MC68306 USER'S MANUAL
S2
9
S3
47
S4
S5
27
S6
S7
S0
3- 35