MC68306 Motorola, MC68306 Datasheet - Page 140

• Manufacturer Part Number: MC68306
• Description: Integrated EC000 Processor
• Manufacturer: Motorola

DBB—Delta Break B
RxRDYB—Channel B Receiver Ready or FIFO Full
TxRDYB—Channel B Transmitter Ready
CTR/TMR_RDY—Counter/Timer Ready
DBA—Delta Break A. See DBB.
RxRDYA—Channel A Receiver Ready or FIFO Full. See RxRDYB.
TxRDYA—Channel A Transmitter Ready. See TxRDYB.
6.4.1.11 INTERRUPT MASK REGISTER (DUIMR). The DUIMR selects the corresponding
bits in the DUISR that cause an interrupt output (IRQ ). If one of the bits in the DUISR is
set and the corresponding bit in the DUIMR is also set, the IRQ output is asserted. If the
corresponding bit in the DUIMR is zero, the state of the bit in the DUISR has no effect on
the IRQ output. The DUIMR does not mask the reading of the DUISR.
COS—Change-of-State
6-32
This bit is the duplication of the TxRDY bit in DUSRB.
The function of this bit is programmed by DUMR1A bit 6.
This bit is the duplication of the TxRDY bit in DUSRA.
1 = The channel B receiver has detected the beginning or end of a received break.
0 = No new break-change condition to report. Refer to 6.4.1.5 Command Register
The function of this bit is programmed by DUMR1B bit 6. It is a duplicate of either the
1 = The transmitter holding register is empty and ready to be loaded with a character.
0 = The transmitter holding register was loaded by the CPU, or the transmitter is
1 = Counter/timer ready.
0 = Counter/timer not ready.
1 = Enable interrupt
0 = Disable interrupt
(DUCR) for more information on the reset break-change interrupt command.
FFULL or RxRDY bit of DUSRB.
disabled. Characters loaded into the transmitter holding register when TxRDYx=0
are not transmitted.
DUIMR
Write Only
RESET:
COS
7
0
DBB
6
0
MC68306 USER'S MANUAL
FFULLB TxRDYB CTR/TM
5
0
4
0
_RDY
3
R
0
DBA
2
0
FFULLA TxRDYA
1
0
0
0
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