MC6800 Motorola, MC6800 Datasheet - Page 7

• Manufacturer Part Number: MC6800
• Description: 8-BIT MICROPROCESSING UNIT (MPU)
• Manufacturer: Motorola

the peripherals
write,
tDB E as shown,
and @,@tfhe
state as a result
such time,
state and other
of a maskable
output
30 pF. If TSC is in the high state,
access
specified.
voltage
of clock variations
turned
state forces the Address
and peripheral
capable
three-state
enable
TTL compatible;
driven
the data
desired
Direct
held low.
setup
mally
high.?ata~:+indicating
HALT~ne
processor
and timing
tions
the state of the processor.
are used for a two-phase
the VCC voltage
is specified
The allowable
The minimum
by PW~H
dress bus. The outputs
driving
MPU to be used in DMA applications.
It is bidirectional,
Bus is placed
Figure
Read/Write
Address Bus (AOA15)
Data Bus (DO-D7)
Data Bus Enable (DBE)
If additional
Bus Ay~i$~l~.(bA)
Clocks Phase One and Phase Two (o1, 42)
Figure
Proper operation
* “’“’*’l+
and that
~%~
or hold t~,$@#
the
Memory
by the phase two
3 (DBE#@2\R:~~e~inimum
one standard
off,
the bus drivers
..,*.’:* Y
time
is capable
of VOV (overlap
that another
of driving
bus drivers
1 shows
is removed
(pulse width
Clock
is in the low state or the processor
DB E
all three-state
signals
it is essentially
control
;>L:.,.?J ~ ,
~}$’low
at VIHC
for the peripherals,
address
@l and @2 high level pulse widths
in the three-state
(mask bit I = O) or nonmaskable
data setup+p[+ho~d~?me
(R/~)
clock frequency
devices.
other
and memory
Access
outputs
\\\$.
down ,~,~~ @n be decreased, as shown in
of the execution
separation,
~~~.s}~ting
however
level.
transferring
the microprocessor
one standard
at the system
be provided
of driving
of the MPU requires
signal
state;
TTL load and 90 pF. When
device
and the low level is specified
– Eight pins are used for the data bus.
signal
from the WAIT
will
that
bus is available.
– This TTL compatible
@
–
when
high time).
are three-state
be increased.
It also has three-state
(DMA)j+~k~@~ions,
to their normally
voltage),
bus to go into the three-state
– Sixteen
clock.
The Bus Available
non-overlapping
be disabled,’~~t~nal
output
– This level sensitive
when
the microprocessor
an open circuit.
for
in normal
lines be monitored
contr$PtR~&ata
devices
.>.:,:,.,,
td, is measured
in the high st~:&$$@j9
data to and from
one
D B E with
the
,
is specified
to accomplish
MOTOROLA
mode
Durin&@n~~,K~
TTL load and 130 pF. D,a~$,
activated,
~t~
frequency
drivers
the clock
,x .
of a WAIT
This allows
Bus Available
To guarantee
M PU data
standard
pins are used for the ad-
wether
state by the occurrence
down
op~,atib~~$twould
Putting
is required
clocks.
bus drivers capable
when
This will
that certain
will
respect
inactive
clock that runs at
by f (frequency).
This permits
time
it will
the MPU is in a
up time,
rate.
bus, such as in
DBE is Io#t\,t
DBE should
signal
instruction.
go to their
TTL
is in the WAIT
at a maximum
for a multitude
TSC in its high
interrupt,
output
output
ly. When
The high level
specific
~$~l:~yd
to determine
has stopped
the output
are specified
–
the memory
occur
MPU SIGNAL DESCRIPTION
the required
will be low,
i~[~t~$sthe
on an MPU
read cycle,
for DBE is
to E, data
level. The
go to the
Two
load
.+,. ‘+:+” ‘ ‘$,. ?
at VILC.
will
Input
signals
buffer$
,{’.y...:>.:>
control
mode.
tut,
if the
func-
This
nor-
pins
and
,,:!:.?..
it is
will
the
off
be
At
be
of
is
is
is
w~$.
Semiconductor
7
.lp~
?$:jlj$~qtiired
‘~trestarting.
~i. ~,P@
terrupt
the request.
dition
terrupt
cumulators,
the stack.
quest by setting
interrupts
dress will be loaded
is located
loaded
Figure 9.
quests
machine.
rent instruction
which
with
with the MPU system
to
cycles
followinqj$&MVMA=
con$&8
determinate
battery-backed
low after
fall transition
is high at tpcs
begin
may also be used to reinitialize
during
low
cycles.
if setup
when
90 pF.
failure
input
after start-up.
MPU
quence,
in memory
routine,
under program
IRQ. While
peda~~e,>~~~=
&“~q@~nce
RESET timing
Figure
this signal is Read (high).
turn
output
M PU from
Read (high) or Wrile
Interrupt
RESET
If a high level is detected
the
for the duration
the system
Read/Write
can also be used to reinitialize
Code Register
?}4
the processor
on the next cycle as shown.
to
at these locations
or initial
have ~Jcc~$r8d) the MPU output
could
sequence.
8, in any given
its operation.
that
reaches 4.75 V, a minimum
routine
The RESET
beginning
is capable
the ‘reset address
time tpcs
the contents
the interrupt
for the processor to stabilize
The processor
eight
begin
may occur.
in memory
– The RESET input
Next,
During
will be loade@{~~&,Jtie
a power
Request
‘K%Jk’’low
an interrupt
At that time,
and Condition
state so any devices
accept
using the RESET control line. After the power
times are specified
is shown
c~~ol,
start-up
cycles.
RAM)
the interrupt
that
in memory.
(processor
the
clock any time after the eighth
the MPU
high (read state),
The Index Register,
to the off
Products Inc.
these eight
of..,$~b.:wet
is met.
that points
of drivina
pulse
is not set, the machine
down
is halted,
a false write
This is accomplished
(~Q)
is being
(low) state, The normal
~.\J ~t.~,,~y..
reset
locations
of th,~?%f$wb
clock and will be recognized
of a minimum
~s~
At the end of the cycle,
must be disabled
before the M PU can be interrupted
RESET can go high asynchronously
cycle then
of the processor,+:~@l%~i&el
in Figure 8. The maximum
will wait
causes the MPU to branch to an in-
low,
sequence
if the interrupt
Three-State
FFFE. Figure 8 illustrates
can be completely
Code Register
(assuming a minimum of8 clock
condition
seqe~$~.
will
control
–
in th~
mask bit high so that no further
bit is set and must
Interrupt
executed
(high
BA=
cycles,
This
it will be in the off state.
to a vectoring
one
the MPU system
respond
FFF8 and FFF9. An address
is used to rese~&}N~&~rt
by tpcr
routine.
until
that
Program
during
the restart
and the Address
setup
be generated
low,
:t:;l,\
Inpw;
.)’
of eight clock cycles are
impedance)
standard
level sensitive
t,$~~~~~ne
The RESET
resulti~~,jf~%
locations
Program
of three
Control
VMA
During
it completes
are enabled
k%}?*
timing
signals
before
mask bit in the Con-
until VMA
to the interrupt
Data Bus=
\
and tpcf.
are stored away on
time),
in preparation
this time
this will signal
by pulsing
During
Counter
will begin an in-
will
standby
address which
TTL
going
asynchronous
sequence
the
Counter,
it recognizes
is shown
(FFFE, FFFF)
will be in the
complete
a 16-bit ad-
as shown
state.
be in an in-
cycle.
control
at any time
at any time
within
be cleared
during
the
input
reset
If RESET
Ioa&?iqnd
is forced
~+,r+i~
by VMA
(such
sensitive
a power
the cur-
a power
high im-
high will
rise and
to point
Bus will
state of
RESET
Also,
.:}
reset
This
Ac-
the
will
line
the
re-
the
for
re-
se-
42
42
by
as
in
in