MC6800 Motorola, MC6800 Datasheet - Page 13

• Manufacturer Part Number: MC6800
• Description: 8-BIT MICROPROCESSING UNIT (MPU)
• Manufacturer: Motorola

ferent executable
and decimal arithmetic,
conditional
manipulation
on the addressing mode. (The addressing modes which are
available for use with the various executive instructions
discussed later, )
executable instruction
and the addressing mode. The hexadecimal equivalents of
the binary codes, which result from the translation of the 72
instructions
Table 1. There are 197 valid machine codes, 59 of the 256
possible codes being unassigned.
MWW
brief
MC~
language assembles into 1 to 3 bytes of machine code. The
number of bytes depends on the particular instruction
30
31
12
3A
3B
3C
?D
3E
3F
10
11
12
13
14
15
16
17
18
19
1A
IB
Ic
ID
IE
IF
20
21
22
23
24
25
2a
27
2a
29
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
The MC~
The coding of the first (or only) byte corresponding
Each of the 72 executable
NOP
TAP
TPA
CLV
SEV
CLC
SEC
TAB
INX
DEX
CLI
SEI
SBA
CBA
TBA
DAA
ABA
BRA
BHI
PUL
PUL
DES
TXS
PSH
PSH
.
RTS
“
RTI
“
.
WAI
Swl
introduction
Programming
control programs. The MC66W has a set of 72 dif-
A
B
A
B
or unconditional
in all valid modes of addressing, are shown in
instructions.
REL
REL
REL
REk
instructions
source instructions.
and discuss
40
41
42
43
44
45
4a
47
48
49
4A
40
4C
4D
4E
4F
50
51
52
53
54
55
5a
57
5a
59
5A
5B
5C
5D
5E
5F
ao
ac
ao
aE
6F
70
71
72
73
74
75
7a
79
77
78
7A
7B
7C
7D
7E
7F
m
Manual.
is sufficient to identify the instruction
logical, shift,
NEG
COM
LSR
ROR
ASR
ASL
ROL
DEC
TST
INC
CLR
NEG
COM
LSR
ROR
ASR
ASL
ROL
DEC
INC
TST
TST
JMP
COM
ASR
ASL
INC
CLR
N EG
.
.
LSR
.
ROR
ROL
DEC
.
INC
TST
JMP
CLR
are described in detail in the
branch,
MOTOROLA
This Section will provide a
instructions
A
A
A
A
A
A
A
A
A
A
A
B
B
B
B
B
B.
their
IND
IND
INO
IND
INO
IND
IND
(ND
INO
IND
IND
IND
EXT
EXT
EX1
EXT
EX1
EX1
EX1
EX1
EX1
EX1
EX1
EX1
interrupt
Included are binary
rotate,
use in developing
80
81
82
83
84
85
88
87
8a
a9
8A
aB
ac
8D
8E
8F
90
91
92
93
QA
9D
9E
9F
AO
Al
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
BO
B1
B2
B3
B4
B5
Ba
B7
Ba
B9
BA
BB
BC
BD
BE
BF
of the source
SUB
CMP
SBC
AND
BIT
LDA
EOR
LDS
STS
sua
CMP
SBC
AND
BIT
LDA
STA
ADC
ORA
ADD
CPX
JSR
LDS
STS
SUB
CMP
SBC
AND
BIT
LDA
STA
EOR
ADC
ORA
ADD
CPX
JSR
LOS
STS
EOR
load, store,
and stack
MPU INSTRUCTION
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
to an
and
are
DIR
DIR
DIR
IND
[ND
IND
IND
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
IMM
IMM
IMM
IMM
IMM
IMM
IMM
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
IND
IND
IND
IND
lND
IND
IND
IND
IND
IND
IND
EXT
EXT
EXT
EXT
EXT
EXT
EXT
Semiconductor
13
co
cl
C2
C3
C4
C5
ca
C7
C8
CE
CF
DO
01
D2
D3
D4
D5
D6
D7
Da
D9
DA
DB
DC
DD
DE
DF
EO
El
E2
E3
E4
E5
Ea
E7
E8
E9
EA
EB
EC
ED
EE
EF
FO
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
LDX
.
SUB
CMP
SBC
“
AND
BIT
LDA
STA
EOR
ADC
ORA
ADD
‘
.
LDX
STX
SUB
CMP
SBC
.
AND
BIT
LDA
STA
EOR
ADC
ORA
ADD
.
.
LDX
STX
SUB
CMP
SBC
.
AND
BIT
LDA
STA
EOR
ADC
ORA
ADD
“
.
LDX
STX
tain(s) an operand, an address, or information
address is obtained during execution.
general
operating
tion
adapters (PIA and ACIA) allow the MPU t~$~~~k~peripheral
devices exactly like other memory loca@~$.3@#nce, no 1/0
instructions as such are required. Beca&Wq@these features,
other classifications
operations;
code, the second byte, or the second and third bytes con-
because they operate on specific
memory reference; (3) 1/0 instructions
between the microprocessor
memory
MC66WS
Code Register operations, ,,,~~~~, %
When an instruction
Microprocessor
In many instances, the M Cm
SET
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
a
B
B
B
B
B
a
on both
classifications:
IMM
IMM
IMM
IMM
IMM
OIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
IND
IND
IND
IND
IND
IND
IND
IND
IND
IND
IND
IND
IND
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
locations.
instructions
instruction
(2) Program cont~~t~perations;
its internal
Products Inc.
Notes:
instructions
are more sui~@fl~&~~b~ i ntroducing
In addition,
.t;~..
set: (1) ,$cc’%hlator
, ,\<!\{ .i$’ ‘ ~,, ~:li
translates into two or three bytes of
2. Unassign4
1 Addressing Modes:
that
(1) memory
‘*+\., ~~i,
~~-~ ,,, ,.,,\.,
accumulators
and peripheral devices.
function
~ i~~~
A=
B
REL
INO
IMM
DIR
are often divided into three
performs the sarn”$*a-
code indicated by J # * )‘.
the
= Accumulator B
= Relative
= Indexed
= Immetiate
= Direc?
memory
Accumulator A
reference,
without
for transferring
‘$,? ~
MC%:,~@terface
and ~#r@rnal
from which an
locations;
(3) Condition
and
needing
so called
memory
$+cl+
data
the
(2)
a