ADE7758 Analog Devices, ADE7758 Datasheet - Page 59

• Manufacturer Part Number: ADE7758
• Description: Poly Phase Multifunction Energy Metering IC with Per Phase Information
• Manufacturer: Analog Devices

Address
[A6:A0]
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
Name
CVRMS
FREQ
TEMP
WFORM
OPMODE
MMODE
WAVMODE
COMPMODE
LCYCMODE
MASK
STATUS
RSTATUS
ZXTOUT
LINECYC
SAGCYC
SAGLVL
VPINTLVL
IPINTLVL
VPEAK
IPEAK
R/W
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R
R
1
Length
24
12
8
24
8
8
8
8
8
24
24
24
16
16
8
8
8
8
8
8
Default
Value
0
0
0
0
4
0xFC
0
0x1C
0x78
0
0
0
0xFFFF
0xFFFF
0xFF
0
0xFF
0xFF
0
0
Description
Phase C Voltage Channel RMS Register.
Frequency of the Line Input Estimated by the Zero-Crossing Processing. It can
also display the period of the line input. Bit 7 of the LCYCMODE register
determines if the reading is frequency or period. Default is frequency. Data Bit 0
and Bit 1 of the MMODE register determine the voltage channel used for the
frequency or period calculation.
Temperature Register. This register contains the result of the latest temperature
conversion. Please refer to the Temperature Measurement section for details on
how to interpret the content of this register.
Waveform Register. This register contains the digitized waveform of one of the
six analog inputs or the digitized power waveform. The source is selected by
Data Bit 0 to Bit 4 in the WAVMODE register.
Operational Mode Register. This register defines the general configuration of the
ADE7758 (see Table 14).
Measurement Mode Register. This register defines the channel used for period
and peak detection measurements (see Table 15).
Waveform Mode Register. This register defines the channel and sampling
frequency used in the waveform sampling mode (see Table 16).
This register configures the formula applied for the energy and line active energy
measurements (see Table 17).
This register configures the Line Cycle Accumulation Mode for WATT-HR, VAR-HR,
and VA-Hr (see Table 18).
The IRQ Mask Register. It determines if an interrupt event generates an active-
low output at the IRQ pin (see the ADE7758 Interrupts section).
The IRQ Status Register. This register contains information regarding the source
of the ADE7758 interrupts (see the ADE7758 Interrupts section).
Same as the STATUS Register, except that its contents are reset to 0 (all flags
cleared) after a read operation.
Zero-Cross Timeout Register. If no zero crossing is detected within the time
period specified by this register, the interrupt request line (IRQ) goes active low
for the corresponding line voltage. The maximum timeout period is 2.3 seconds
(see the Zero-Crossing Detection section).
Line Cycle Register. The content of this register sets the number of half-line
cycles that the active, reactive, and apparent energies are accumulated for in the
line accumulation mode.
SAG Line Cycle Register. This register specifies the number of consecutive half-
line cycles where voltage channel input may fall below a threshold level. This
register is common to the three line voltage SAG detection. The detection
threshold is specified by the SAGLVL register (see the Line Voltage SAG Detection
section).
SAG Voltage Level. This register specifies the detection threshold for the SAG
event. This register is common to all three phases’ line voltage SAG detections.
See the description of SAGCYC register for details.
Voltage Peak Level Interrupt Threshold Register. This register sets the level of the
voltage peak detection. Bit 5 to Bit 7 of the MMODE register determine which
phases are to be monitored. If the selected voltage phase exceeds this level, the
PKV flag in the IRQ status register is set.
Current Peak Level Interrupt Threshold Register. This register sets the level of the
current peak detection. Bit 5 to Bit 7 of the MMODE register determine which
phases to are be monitored. If the selected current phase exceeds this level, the
PKI flag in the IRQ status register is set.
Voltage Peak Register. This register contains the value of the peak voltage
waveform that has occurred within a fixed number of half-line cycles. The
number of half-line cycles is set by the LINECYC register.
Current Peak Register. This register holds the value of the peak current waveform
that has occurred within a fixed number of half-line cycles. The number of half-
line cycles is set by the LINECYC register.
Rev. A | Page 59 of 68
ADE7758