ADE7758 Analog Devices, ADE7758 Datasheet - Page 56

• Manufacturer Part Number: ADE7758
• Description: Poly Phase Multifunction Energy Metering IC with Per Phase Information
• Manufacturer: Analog Devices

ADE7758
The communications register is an 8-bit write-only register. The
MSB determines whether the next data transfer operation is a
read or a write. The seven LSBs contain the address of the register
to be accessed. See Table 12 for a more detailed description.
Figure 89 and Figure 90 show the data transfer sequences for a
read and write operation, respectively.
On completion of a data transfer (read or write), the ADE7758
once again enters into communications mode, i.e., the next
instruction followed must be a write to the communications
register.
DOUT
SCLK
A data transfer is completed when the LSB of the ADE7758
register being addressed (for a write or a read) is transferred to
or from the ADE7758.
ADE7758 SERIAL WRITE OPERATION
The serial write sequence takes place as follows. With the
ADE7758 in communications mode and the CS input logic low,
a write to the communications register takes place first. The
SCLK
DIN
DIN
CS
CS
Figure 89. Reading Data from the ADE7758 via the Serial Interface
COMMUNICATIONS REGISTER WRITE
COMMUNICATIONS REGISTER WRITE
SCLK
DIN
Figure 90. Writing Data to the ADE7758 via the Serial Interface
CS
1
0
ADDRESS
ADDRESS
SCLK
DIN
t
1
1
X
A6
t
2
X
A5
t
3
COMMAND BYTE
MULTIBYTE
MULTIBYTE READ DATA
MOST SIGNIFICANT BYTE
A4
X
t
4
A3
X
t
READ DATA
5
DB11
A2
Figure 91. Serial Interface Write Timing Diagram
Figure 92. 12-Bit Serial Write Operation
A1
DB10
A0
DB9
Rev. A | Page 56 of 68
t
7
DB8
DB7
DB7
MOST SIGNIFICANT BYTE
MSB of this byte transfer must be set to 1, indicating that the
next data transfer operation is a write to the register. The seven
LSBs of this byte contain the address of the register to be written
to. The ADE7758 starts shifting in the register data on the next
falling edge of SCLK. All remaining bits of register data are
shifted in on the falling edge of the subsequent SCLK pulses
(see Figure 91).
As explained earlier, the data write is initiated by a write to the
communications register followed by the data. During a data
write operation to the ADE7758, data is transferred to all on-
chip registers one byte at a time. After a byte is transferred into
the serial port, there is a finite time duration before the content
in the serial port buffer is transferred to one of the ADE7758
on-chip registers. Although another byte transfer to the serial
port can start while the previous byte is being transferred to the
destination register, this second-byte transfer should not finish
until at least 900 ns after the end of the previous byte transfer.
This functionality is expressed in the timing specification t
Figure 91). If a write operation is aborted during a byte transfer
( CS brought high), then that byte is not written to the
destination register.
Destination registers may be up to 3 bytes wide (see the
Accessing the ADE7758 On-Chip Registers section). Therefore,
the first byte shifted into the serial port at DIN is transferred to
the most significant byte (MSB) of the destination register. If
the destination register is 12 bits wide, for example, a two-byte
data transfer must take place. The data is always assumed to be
right justified; therefore, in this case, the four MSBs of the first
byte would be ignored and the four LSBs of the first byte written
to the ADE7758 would be the four MSBs of the 12-bit word.
Figure 92 illustrates this example.
DB6
DB5
LEAST SIGNIFICANT BYTE
DB4
DB0
DB3
t
7
DB2
LEAST SIGNIFICANT BYTE
DB7
DB1
t
6
DB0
DB0
t
8
6
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