CY8C25122 Cypress Semiconductor, CY8C25122 Datasheet - Page 110

• Manufacturer Part Number: CY8C25122
• Description: 8-Bit Programmable System-on-Chip (PSoC) Microcontrollers
• Manufacturer: Cypress Semiconductor

Table 88:
Accumulator Result 3 / Multiply/Accumulator Clear 0 Register (ACC_DR3 / MAC_CL0, Address = Bank 0, EEh)
Table 89:
Accumulator Result 2 / Multiply/Accumulator Clear 1 Register (ACC_DR2 / MAC_CL1, Address = Bank 0, EFh)
11.2
The output of a ∆−Σ modulator is a high-speed, single bit
A/D converter. A single bit A/D converter is of little use to
anyone and must be converted to a lower speed multiple
bit output. Converting this high-speed single bit data
stream to a lower speed multiple bit data stream requires
a data decimator.
110
Bit [7:0] : Data [7:0]
8-bit data value when read is the highest order result of the multiply/accumulate function
Any 8-bit data value when written will cause all four Accumulator result registers to clear
Bit [7:0] : Data [7:0]
8-bit data value when read is next to highest order result of the multiply/accumulate function
Any 8-bit data value when written will cause all four Accumulator result registers to clear
Read/Write
Read/Write
Bit Name
Bit Name
Bit #
POR
Bit #
POR
Decimator
Accumulator Result 3 / Multiply/Accumulator Clear 0 Register
Accumulator Result 2 / Multiply/Accumulator Clear 1 Register
Data [7]
Data [7]
RW
RW
7
0
7
0
Data [6]
Data [6]
RW
RW
Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
6
0
6
0
0
n
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
Coeff
Figure 29: Decimator Coefficients
0
Data [5]
Data [5]
RW
RW
5
0
5
0
Data [4]
n-1
Data [4]
RW
4
0
RW
4
0
A “divide by n” decimator is a digital filter that takes the
single bit data at a fast rate and outputs multiple bits at
one n
optimal filter has a sinc
implemented as a finite impulse response (FIR) filter and
for a “divide by n” implementation should have the follow-
ing coefficients:
th
Data [3]
the speed. For a single stage ∆−Σ converter, the
RW
Data [3]
3
0
RW
3
0
2n-1
Data [2]
t
RW
Data [2]
2
0
RW
2
2
0
response. This filter can be
Data [1]
RW
Data [1]
1
0
RW
1
0
September 5, 2002
Data [0]
Data [0]
RW
RW
0
0
0
0