SAA7380GP Philips Semiconductors, SAA7380GP Datasheet - Page 5

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SAA7380GP

Manufacturer Part Number
SAA7380GP
Description
Error correction and host interface IC for CD-ROM ELM
Manufacturer
Philips Semiconductors
Datasheet
Philips Semiconductors
6
1996 Apr 25
DGND1
RA6
RA7
RA8
RA9
RA10
RA11
RA12
RA13
RA14
RA15/RAS
RA16/CAS
RWE
DGND2
RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7
TEST2
DGND3
TEST1
CROUT
CRIN
SFSY
RCK
SUB
BCK
V
WS
DATA
C2PO
SDA
SCL
INT
RESET
SYN
DDD1
Error correction and host interface IC for
CD-ROM (ELM)
PINNING
SYMBOL
PIN
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
11
1
2
3
4
5
6
7
8
9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
digital ground 1
buffer RAM address bus output line 6
buffer RAM address bus output line 7
buffer RAM address bus output line 8
buffer RAM address bus output line 9
buffer RAM address bus output line 10
buffer RAM address bus output line 11 (SRAM) only
buffer RAM address bus output line 12 (SRAM) only
buffer RAM address bus output line 13 (SRAM) only
buffer RAM address bus output line 14 (SRAM) only
buffer RAM address bus output line 15 (SRAM) or RAS (DRAM)
buffer RAM address bus output line 16 (SRAM) or CAS (DRAM)
buffer RAM write enable output
digital ground 2
buffer RAM data bus bidirectional line 0
buffer RAM data bus bidirectional line 1
buffer RAM data bus bidirectional line 2
buffer RAM data bus bidirectional line 3
buffer RAM data bus bidirectional line 4
buffer RAM data bus bidirectional line 5
buffer RAM data bus bidirectional line 6
buffer RAM data bus bidirectional line 7
test input 2
digital ground 3
test input 1
clock oscillator output
clock oscillator input
serial subcode input frame sync input
serial subcode clock output (active LOW)
serial input for Q-to-W subcode input
serial interface bit clock input
digital supply voltage 1 (3.3 V)
serial interface word clock input
serial data input
serial interface flag input
sub-CPU serial data input/output
sub-CPU serial clock input
sub-CPU open-collector interrupt output
power-on reset input (active LOW)
sync signal input from sub-CPU
5
DESCRIPTION
Preliminary specification
SAA7380

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