SAA7380GP Philips Semiconductors, SAA7380GP Datasheet - Page 16

• Manufacturer Part Number: SAA7380GP
• Description: Error correction and host interface IC for CD-ROM ELM
• Manufacturer: Philips Semiconductors

Philips Semiconductors
7.7.12
Resetting the chip sets all the bits in this register to logic 0.
Table 6 CTRL0 register
1996 Apr 25
Error correction and host interface IC for
CD-ROM (ELM)
BIT
7
6
5
4
3
2
1
0
CTRL0
lookahead
ERAMRQ
AUTORQ
ENCODE
ECCRQ
DECEN
E01RQ
WRRQ
NAME
Disable decoding = 0; Enable decoding = 1. This bit enables/disables decoding
functions. Disabling the decoding functions also disables the decoder interrupt.
At interrupt PT, header refer to current block = 0; At interrupt PT, header refer to next
block = 1. When this bit is set to logic 1 at decoder interrupt, CMA and header registers
will give information on the next block instead of on the current block. The lookahead
mode was included to provide support for bad RAMs, and to give the CPU better control
on the blocks it wants to read.
Disable error correction of bytes = 0; Enable correction of CIRC mis-corrections = 1.
Setting this bit to logic 0 instructs the error corrector not to correct bytes flagged as
reliable by the CIRC error corrector.
Disable automatic error correction = 0; Enable automatic error correction = 1. Requests
automatic extraction of form bit during Mode 2 correction from sub-header data.
Disable erasure flag use = 0; Enable erasure flag use = 1. When set to logic 1, the
SAA7380 will enable the use of erasure flag information for error correction. When set to
logic 0, the SAA7380 will disable the use of erasure flag information for error correction.
Use of erasure flags must be disabled when the CD-DSP does not output erasure flags
and when the internal buffer RAM is disabled (which is necessary for repeat correction).
Disable data writes to the buffer and PTL updates = 0; Enables data writes to the buffer
and PTL updates = 1. This bit enables/disables writes from the CD drive into the buffer. It
also enables/disables pointer (PTL, PTH and PTHH) updates each time a block is
received. When WRRQ is set to logic 1, data write will start from the first byte of the next
block onwards. When WRRQ is set to logic 0, repeat correction is enabled. With WRRQ
set to logic 0, the internal buffer RAM is disabled.
Disable ECC correction = 0; Enable ECC correction = 1. When ECCRQ is set to logic 1
the blocks received by the SAA7380 will be error corrected before a decoder interrupt is
generated. When ECCRQ is set to logic 0 no corrections are performed. The algorithm
used is a QD, PD, QE, PE algorithm. In a first step, errors are corrected; in a second
step, erasures are corrected. Correction data is read from the on-chip 36 kbit buffer
memory.
Normal operation = 0; Test mode, do not use = 1, this bit must always be set to logic 0.
16
FUNCTION
Preliminary specification
SAA7380