DAC0830LCM National Semiconductor, DAC0830LCM Datasheet - Page 8

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DAC0830LCM

Manufacturer Part Number
DAC0830LCM
Description
8-Bit P Compatible/ Double-Buffered D to A Converters
Manufacturer
National Semiconductor
Datasheet

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Typical Performance Characteristics
Gain and Linearity Error
Variation vs. Supply Voltage
DAC0830 Series Application Hints
These DAC’s are the industry’s first microprocessor compat-
ible, double-buffered 8-bit multiplying D to A converters.
Double-buffering allows the utmost application flexibility from
a digital control point of view. This 20-pin device is also pin
for pin compatible (with one exception) with the DAC1230, a
12-bit MICRO-DAC. In the event that a system’s analog out-
put resolution and accuracy must be upgraded, substituting
the DAC1230 can be easily accomplished. By tying address
bit A
precision) which automatically increments the address for
the second byte write (starting with A
This allows either an 8-bit or the 12-bit part to be used with
no hardware or software changes. For the simplest 8-bit ap-
plication, this pin should be tied to V
in section 1.1).
Analog signal control versatility is provided by a precision
R-2R ladder network which allows full 4-quadrant multiplica-
tion of a wide range bipolar reference voltage by an applied
digital word.
1.0 DIGITAL CONSIDERATIONS
A most unique characteristic of these DAC’s is that the 8-bit
digital input byte is double-buffered. This means that the
data must transfer through two independently controlled 8-bit
latching registers before being applied to the R-2R ladder
network to change the analog output. The addition of a sec-
ond register allows two useful control features. First, any
DAC in a system can simultaneously hold the current DAC
data in one register (DAC register) and the next data word in
the second register (input register) to allow fast updating of
the DAC output on demand. Second, and probably more im-
portant, double-buffering allows any number of DAC’s in a
system to be updated to their new analog output levels si-
multaneously via a common strobe signal.
0
to the ILE pin, a two-byte µP write instruction (double
DS005608-29
CC
0
(also see other uses
= “1”) can be used.
Write Pulse Width
(Continued)
8
The timing requirements and logic level convention of the
register control signals have been designed to minimize or
eliminate external interfacing logic when applied to most
popular microprocessors and development systems. It is
easy to think of these converters as 8-bit “write-only”
memory locations that provide an analog output quantity. All
inputs to these DAC’s meet TTL voltage level specs and can
also be driven directly with high voltage CMOS logic in
non-microprocessor based systems. To prevent damage to
the chip from static discharge, all unused digital inputs
should be tied to V
are inadvertantly left floating, the DAC interprets the pin as a
logic “1”.
1.1 Double-Buffered Operation
Updating the analog output of these DAC’s in a
double-buffered manner is basically a two step or double
write operation. In a microprocessor system two unique sys-
tem addresses must be decoded, one for the input latch con-
trolled by the CS pin and a second for the DAC latch which
is controlled by the XFER line. If more than one DAC is being
driven, Figure 2 , the CS line of each DAC would typically be
decoded individually, but all of the converters could share a
common XFER address to allow simultaneous updating of
any number of DAC’s. The timing for this operation is shown,
Figure 3 .
It is important to note that the analog outputs that will change
after a simultaneous transfer are those from the DAC’s
whose input register had been modified prior to the XFER
command.
DS005608-30
CC
Data Hold Time
or ground. If any of the digital inputs
DS005608-31

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