LM1246AAA National Semiconductor, LM1246AAA Datasheet - Page 41

• Manufacturer Part Number: LM1246AAA
• Description: 150 MHz I2C Compatible RGB Preamplifier with Internal 512 Character OSD ROM/ 512 Character RAM and 4 DACs
• Manufacturer: National Semiconductor

Pre-Amplifier Interface Registers
Global Video Control:
Auxiliary Control:
PLL Range:
Bit 5
Bit 6
Bit 7
Bit 0
Bit 1
Bit 2
Bits 7–3
Bit 0
Bit 1
Bit 2
Bits 6–3
Bit 7
Bit 1–0
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Reserved
Res’d
X
When this bit is a 0, the full-scale outputs of DACs 1–3 are 0.5V to 4.5V. When it is a 1, the
full-scale level is 0.5V to 2.5V.
When this bit is a 0, the DAC 4 output is independent. When it is a 1, the DAC 4 output is scaled
by 50% and added to the outputs of DACs 1–3.
Reserved and should be set to zero.
When this bit is a 1, the video outputs are blanked (set to black level). When it is a 0, video is not
blanked.
When this bit is a 1, the analog sections of the preamplifier are shut down for low power
consumption. When it is a 0, the analog sections are enabled.
This bit is a 0 by default, where Bank Select is enabled. In this mode, Page RAM addressing is in
the standard mode identical to the LM1247. When this bits a 1, the Bank Select is disabled, and
full 512 character address operation is used.
Reserved.
When this bit is a 0, the horizontal blanking input at pin 24 is gated to the video outputs to provide
horizontal blanking. When it is a 1, the horizontal blanking at the outputs is disabled.
Reserved
When this bit is a 1, the position of the Horizontal Blanking pulse can be programmably varied
relative to the horizontal flyback in number of pixels. When this bit is a 0, which is by default, the
horizontal blanking pulse position will not be programmable.
These 4 bits determine the position of the Horizontal Blanking Pulse with respect to the horizontal
flyback in number of pixels.
Reserved
These bits must be set to 0 to pre-calibrate the PLL Auto feature.
This is the Vertical Blanking register. When this bit is a 1, vertical blanking is gated to the video
outputs. When set to a 0, the video outputs do not have vertical blanking.
This is the OSD override bit. This should be set to 0 for normal operation. When set to a 1, the
video outputs are disconnected and OSD only is displayed. This is useful for the OSD display of
special conditions such as “No Signal” and “Input Signal Out of Range”, to avoid seeing
unsynchronized video.
Reserved and should be set to zero.
This is the Clamp Polarity bit. When set to a 0, the LM1246 expects a positive going clamp pulse.
When set to a 1, the expected pulse is negative going.
When this bit is set, the PLL Auto Mode will automatically determine the optimum frequency range
of the Phase Locked Loop.
X
X
Auto Mode
PLL_AUTO
PLL
Horizontal Blank Position
X
HBPOS[30]
X
Clamp
CLMP
PLLFREQRNG (0x843E)
GLOBALCTRL (0x8439)
AUXCTRL (0x843A)
(Continued)
X
Res’d
X
41
X
OSD
OOR
HBPOS_EN
H. Blank
Bank
BSD
V Blank
VBL
Power
PS
Reserved
Pre-calibration
X
PFR[1:0]
Blank
PLL
BV
H Blnk
HBD
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