LM1246AAA National Semiconductor, LM1246AAA Datasheet - Page 29

• Manufacturer Part Number: LM1246AAA
• Description: 150 MHz I2C Compatible RGB Preamplifier with Internal 512 Character OSD ROM/ 512 Character RAM and 4 DACs
• Manufacturer: National Semiconductor

Register
FRMCTRL1
FRMCTRL2
CHARFONTACC
VBLANKDUR
CHARHTCTRL
BBHLCTRLB0
BBHLCTRLB1
BBLLCTRLB0
BBLLCTRLB1
CHSDWCTRLB0
CHSDWCTRLB1
ROMSIGCTRL
ROMSIGDATAB0
ROMSIGDATAB1
HSTRT1
VSTRT1
W1STRTADRL
W1STRTADRH
COLWIDTH1B0
COLWIDTH1B1
COLWIDTH1B2
COLWIDTH1B3
HSTRT2
VSTRT2
W2STRTADRL
W2STRTADRH
COLWIDTH2B0
COLWIDTH2B1
COLWIDTH2B2
LM1246 Address Map
Note that the pixels in the first line immediately below the character may be overwritten by the pixel override system that creates
the button box. (Refer to the Button Box Formation Section for more information).
After the first line, each new line always starts with an SL code, even if the number of skipped lines to follow is zero. This means
an SL code must always follow an EOL code. An EOL code may follow an SL code if several ’transparent’ lines are required
between sections of the window. See example 3 below for a case where skipped lines of zero characters are displayed, resulting
in one window being displayed in two segments.
End-Of-Screen Code
To signify the end of the window, a special End-Of-Screen (EOS) code is used in place of a End-Of-Line (EOL) code. There must
be at least one EOS code in the Page RAM to avoid unpredictable behavior. This can be accomplished by clearing the RAM by
writing a 0 to bit 3 of the FRMCTRL1 Register, 0x8400, immediately after power up.
Bits 8–0 are all zeros. Bits 12–9 will have the previously entered AC but this is not used and so these bits are “don’t cares”.
OSD CONTROL REGISTERS
These registers, shown in Table 13. OSD Control Register Detail, control the size, position, enhanced features and ROM bank
selection of up to two independent OSD windows. Any bits marked as “X” are reserved and should be written to with zeros and
should be ignored when the register is read. Additional register detail is provided in the Control Register Definitions Section, later
in this document.
ATTRIBUTE CODE
ATT[3:0]
Address
0x840A
0x840D
0x840E
0x841A
0x841B
0x841C
0x841D
0x841E
0x8400
0x8401
0x8402
0x8403
0x8404
0x8405
0x8406
0x8407
0x8408
0x8409
0x840F
0x8410
0x8411
0x8412
0x8413
0x8414
0x8415
0x8416
0x8417
0x8418
0x8419
Default
0xFF
0x5B
0x98
0x80
0x00
0x10
0x51
0x01
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x62
0x32
0x00
0x00
0x00
0x00
0x00
0x00
0x56
0x00
0x01
0x00
0x00
0x00
(Continued)
TABLE 13. OSD Control Register Detail
HTD
D7
PIXELS_PER_LINE[2:0]
X
X
X
X
X
X
X
X
0
TABLE 12. End-Of-Screen Code
B[1:0]
B[1:0]
B[1:0]
ASZEN
D6
0
X
X
X
X
X
X
X
29
0
FEN
D5
X
X
X
X
X
X
X
END-OF-SCREEN CODE
CHAR_HEIGHT[7:0]
0
G[2:0]
G[2:0]
G[2:0]
VBLANK_DURATION[6:0]
D4
TD
X
X
X
X
X
X
X
COL[23:16]
COL[31:24]
COL[23:16]
HPOS[7:0]
ADDR[7:0]
HPOS[7:0]
ADDR[7:0]
CRC[15:8]
VPOS[7:0]
VPOS[7:0]
COL[15:8]
COL[15:8]
CRC[7:0]
COL[7:0]
COL[7:0]
0
CDPR
D3
X
X
X
X
X
X
X
BLINK_PERIOD[4:0]
0
D2E
D2
X
X
X
X
X
X
X
0
R[2:0]
R[2:0]
R[2:0]
ATTR
D1E
D1
X
X
X
X
X
X
0
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ADDR[8]
ADDR[8]
FONT4
OSE
CRS
B[2]
B[2]
B[2]
D0
0