LM9810CCWM National Semiconductor, LM9810CCWM Datasheet - Page 7

• Manufacturer Part Number: LM9810CCWM
• Description: LM9810/20 10/12-Bit Image Sensor Processor Analog Front End
• Manufacturer: National Semiconductor

Note 7: Two diodes clamp the OS analog inputs to
impedance of the sensor, prevents damage to the LM9810/20 from transients during power-up.
Note 8: To guarantee accuracy, it is required that VA and VD be connected together to the same power supply with separate bypass capacitors at each supply pin.
Note 9: Typicals are at T
Note 10: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 11: Integral non-linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that best fits the actual transfer function of the
ADC.
Note 12: V
a white (full scale) image with respect to the reference level, V
correctable range of pixel-to-pixel V
LM9810/20 can correct for using its internal PGA.
Note 13:
Note 14: Full Channel INL and DNL are tested with CDS disabled, negative signal polarity, and a single OS input with a gain register setting of 1 (000001b) and an offset
register setting of 0 (000000b).
Note 15: The digital supply current (I
The current required to switch the digital data bus can be calculated from: Isw = 2*Nd*Psw*CL*
of each data bit switching, CL is the capacitive loading on each data pin,
6, Psw should be .5, and
ital output pin (
will be drawn through the
Gain
PGA
V
--- -
V
REF
PGA Gain Error is the maximum difference between the measured gain for any PGA code and the ideal gain calculated by using the formula
D5
=
is defined as the CCD OS voltage for the reference period following the reset feedthrough pulse. V
G
-
0
D0
+
) is 20pF and the period of tSampCLK is 1/6MHz or 167ns , then the digital switching current would be 7.2mA. The calculated digital switching current
X
PGA code
-------------------------- -
VD
J
VD
=T
32
A
is nominally 5V, the switching current can usually be calculated from: Isw = 30*CL/tSampCLK. For example, if the capacitive load on each dig-
pin and should be considered as part of the total power budget for he LM9810/20.
=25°C, f
WHITE
where
D
MCLK
) does not include the load, data and switching frequency dependent current required to drive the digital output bus on pins (
variation is defined as the maximum variation in V
X
= 24MHz, and represent most likely parametric norm.
=
G
31
AGND
–
G
0
and
32
----- -
31
REF
.
VA
OS Input
. V
V
as shown below. This input protection, in combination with the external clamp capacitor and the output
RFT
RFT
is defined as the peak positive deviation above V
VD
V
REF
CCD Output Signal
is the digital supply voltage and tSampCLK is the period of the
AGND
VA
7
V
WHITE
TO INTERNAL
CIRCUITRY
VD
WHITE
/tSampCLK where Nd is total number of data pins, Psw is the probability
(due to PRNU, light source intensity variation, optics, etc.) that the
WHITE
is defined as the peak CCD pixel output voltage for
REF
of the reset feedthrough pulse. The maximum
SampCLK
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signal. Since Nd is
D5
-
D0
).